E S I
E S I
ADVANCED INFORMATION
Excel Semiconductor inc.
b7
b6
0
b5
b4
BP2
b3
BP1
b2
BP0
b1
WEL
b0
SRWD
0
WIP
Status Register Write Disable
Block Protect Bits
Write Enable Latch Bit
Write In Progress Bit
Figure 7. Status Register Format
As soon as Chip Select (CS#) is driven High, the
self-timed Write Status Register cycle (whose dura-
Write Status Register (WRSR)
tion is t ) is initiated. While the Write Status Regis-
w
The Write Status Register (WRSR) instruction
allows new values to be written to the Status Regis-
ter. Before it can be accepted, a Write Enable
(WREN) instruction must previously have been
executed. After the Write Enable (WREN) instruc-
tion has been decoded and executed, the device
sets the Write Enable Latch (WEL).
ter cycle is in progress, the Status Register may still
be read to check the value of the Write In Progress
(WIP) bit. The Write In Progress (WIP) bit is 1 dur-
ing the self-timed Write Status Register cycle, and
is 0 when it is completed. At some unspecified time
before the cycle is completed, the Write Enable
Latch (WEL) is reset.
The Write Status Register (WRSR) instruction is
entered by driving Chip Select (CS#) Low, followed
by the instruction code and the data byte on Serial
Data Input (SI).
The Write Status Register (WRSR) instruction
allows the user to change the values of the Block
Protect (BP2, BP1, BP0) bits, to define the size of
the area that is to be treated as read-only, as
defined in Table 1. The Write Status Register
(WRSR) instruction also allows the user to set or
reset the Status Register Write Disable (SRWD) bit
in accordance with the Write Protect (W#) signal.
The Status Register Write Disable (SRWD) bit and
Write Protect (W#) signal allow the device to be put
in the Hardware Protected Mode (HPM). The Write
Status Register (WRSR) instruction cannot be exe-
cuted once the Hardware Protected Mode (HPM) is
entered.
The instruction sequence is shown in Figure 8.
The Write Status Register (WRSR) instruction has
no effect on bits b6, b5, b1 and b0 of the Status
Register. Bits b6, b5 are always read as 0.
Chip Select (CS#) must be driven High after the
eighth bit of the data byte has been latched in. If
not, the Write Status Register (WRSR) instruction is
not executed.
CS#
0
1
0
2
3
4
5
0
6
0
7
1
8
9
10
11 12 13 14
15
SCK
SI
Instruction
Status Register In
0
0
0
0
7
6
5
4
3
2
1
0
MSB
High Impedance
SO
Figure 8. Write Status Register (WRSR) Instruction Sequence
13
Rev. 0D May, 11, 2006
ES25P80
EXCELSEMI [ EXCEL SEMICONDUCTOR INC. ]
