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ES25P80-75IC2Y 参数 Datasheet PDF下载

ES25P80-75IC2Y图片预览
型号: ES25P80-75IC2Y
PDF下载: 下载PDF文件 查看货源
内容描述: 8Mbit的CMOS 3.0伏闪存为75Mhz SPI总线接口 [8Mbit CMOS 3.0 Volt Flash Memory with 75Mhz SPI Bus Interface]
分类和应用: 闪存
文件页数/大小: 35 页 / 436 K
品牌: EXCELSEMI [ EXCEL SEMICONDUCTOR INC. ]
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E S I  
E S I  
ADVANCED INFORMATION  
Excel Semiconductor inc.  
Write Enable (WREN)  
Write Disable (WRDI)  
The Write Enable (WREN) instruction (Figure 4) sets  
the Write Enable Latch (WEL) bit. The Write Enable  
Latch (WEL) bit must be set prior to every Page Pro-  
gram (PP or PPP), Erase (SE, BE or PE) and Write  
Status Register (WRSR) instruction. The Write  
Enable (WREN) instruction is entered by driving  
Chip Select (CS#) Low, sending the instruction code,  
and then driving Chip Select (CS#) High.  
The Write Disable (WRDI) instruction (Figure 5)  
resets the Write Enable Latch (WEL) bit. The Write  
Disable (WRDI) instruction is entered by driving Chip  
Select (CS#) Low, sending the instruction code, and  
then driving Chip Select (CS#) High.  
The Write Enable (WEL) bit is reset under the follow-  
ing conditions :  
- Power-up  
- WRDI instruction completion  
- WRSR instruction completion  
- PP instruction completion  
- SE instruction completion  
- BE instruction completion  
CS#  
0
1
2
3
4
5
6
7
SCK  
SI  
Instruction  
0
0
0
0
0
1
1
0
High Impedance  
SO  
Figure 4. Write Enable ( WREN ) Instruction Sequence  
CS#  
SCK  
SI  
0
1
2
3
4
5
6
7
Instruction  
0
0
0
0
0
1
0
0
High Impedance  
SO  
Figure 5. Write Disable ( WRDI ) Instruction Sequence  
11  
Rev. 0D May, 11, 2006  
ES25P80