XRT86L30
SINGLE T1/E1/J1 FRAMER/LIU COMBO
REV. 1.0.1
TABLE 57: TRANSMIT Sa AUTO
CONTROL REGISTER 2
Register 41
T
RANSMIT Sa AUTO ONTROL
C
R
EGISTER (TSACR2)
0x0132
B
IT
FUNCTION
TYPE
D
EFAULT
DESCRIPTION-OPERATION
5
Reserved
Reserved
-
-
-
-
Reserved
Reserved
CRC report
4
3-2 CRCREP_ENB
R/W
R/W
R/W
0
1
0
CRCDET_ENB
0
0
CRC detection
CRCREC/DET_ENB
CRC report and detect
The following table demonstrates the conditions on receive side which trigger the actions while these bit are
enabled.
TABLE 58: CONDITIONS ON
R
ECEIVE SIDE
W
HEN TSACR1 BITS ENABLED
A
CTIONS - SENDING PATTERN FOR
C
ONDITIONS
A
S
A
5
S
A
6
E
X
x
AIS_1_ENB
AIS_2_ENB
1
0
0
0
0
0
0
1
1
1
0
1
1
1
1111
1111
0000
0000
0001
0010
0011
CRCREP_ENB = 01, CRC reported (E = 0)
CRCREP_ENB = 10, CRC reported
CRCREP_ENB = 11, CRC reported
CRCDET_ENB
0
0
1
1
1
CRCDET/REP_ENB
TABLE 59: TRANSMIT Sa4 REGISTER
Register 42
TRANSMIT Sa4 REGISTER (TSA4R)
0x0133
B
IT
FUNCTION
TYPE
D
EFAULT
DESCRIPTION-OPERATION
7-0 TxSa4[7:0]
R/W
11111111 Sa4
The content of this register sources the transmit Sa4 bits while
TxSa4ENB (register 0x010Ah) is 1 and TxSa4SEL (register
0x0130h) is 1.
Bit 7 is transmitted in frame 2 of the CRC-4 multiframe, bit 6 is in
frame 4, etc.
73
EXAR [ EXAR CORPORATION ]
