XRT86L30
REV. 1.0.1
SINGLE T1/E1/J1 FRAMER/LIU COMBO
LIST OF TABLES
Table 1:: List by Pin Number ............................................................................................................................................. 4
Table 2:: Selecting the Microprocessor Interface Mode .................................................................................................. 21
Table 3:: XRT86L30 Microprocessor Interface Signals that exhibit constant roles in both Intel and Motorola Modes .... 22
Table 4:: Intel mode: Microprocessor Interface Signals ................................................................................................... 22
Table 5:: Motorola Mode: Microprocessor Interface Signals ........................................................................................... 23
Table 6:: Intel Microprocessor Interface Timing Specifications ....................................................................................... 25
Table 7:: Intel Microprocessor Interface Timing Specifications ....................................................................................... 27
Table 8:: Motorola 68K Microprocessor Interface Timing Specifications ......................................................................... 28
Table 9:: XRT86L30 Framer/LIU Register Map ............................................................................................................... 30
Table 10:: Register Summary .......................................................................................................................................... 31
Table 11:: Clock Select Register E1 Mode ...................................................................................................................... 37
Table 12:: Line Interface Control Register T1 Mode ........................................................................................................ 38
Table 13:: General Purpose Input/Output 0 Control Register .......................................................................................... 38
Table 14:: Framing Select Register-E1 Mode .................................................................................................................. 39
Table 15:: Framing Select Register-T1 Mode .................................................................................................................. 40
Table 16:: Alarm Generation Register - E1 Mode ............................................................................................................ 41
Table 17:: Alarm Generation Register -T1 Mode ............................................................................................................. 42
Table 18:: Synchronization MUX Register - E1 Mode ..................................................................................................... 44
Table 19:: Synchronization MUX Register - T1 Mode ..................................................................................................... 45
Table 20:: Transmit Signaling and Data Link Select Register - E1 Mode ........................................................................ 46
Table 21:: Transmit Signaling and Data Link Select Register - T1 Mode ........................................................................ 47
Table 22:: Framing Control Register E1 Mode ................................................................................................................ 48
Table 23:: Framing Control Register T1 Mode ................................................................................................................ 49
Table 24:: Receive Signaling & Data Link Select Register - E1 Mode ............................................................................ 50
Table 25:: Receive Signaling & Data Link Select Register (RS&DLSR) T1 Mode .......................................................... 51
Table 26:: Signaling Change Register 0 - T1 Mode ......................................................................................................... 52
Table 27:: Signaling Change Register 1 .......................................................................................................................... 52
Table 28:: Signaling Change Register 2 .......................................................................................................................... 53
Table 29:: Signaling Change Register 3 .......................................................................................................................... 53
Table 30:: Receive National Bits Register ....................................................................................................................... 53
Table 31:: Receive Extra Bits Register ............................................................................................................................ 54
Table 32:: Data Link Control Register .............................................................................................................................. 55
Table 33:: Transmit Data Link Byte Count Register ........................................................................................................ 56
Table 34:: Receive Data Link Byte Count Register ......................................................................................................... 57
Table 35:: Slip Buffer Control Register ............................................................................................................................ 57
Table 36:: FIFO Latency Register .................................................................................................................................... 58
Table 37:: DMA 0 (Write) Configuration Register ............................................................................................................ 58
Table 38:: DMA 1 (Read) Configuration Register ............................................................................................................ 59
Table 39:: Interrupt Control Register ............................................................................................................................... 60
Table 40:: LAPD Select Register ..................................................................................................................................... 60
Table 41:: Customer Installation Alarm Generation Register .......................................................................................... 61
Table 42:: Performance Report Control Register ............................................................................................................ 61
Table 43:: Gapped Clock Control Register ...................................................................................................................... 62
Table 44:: Gapped Clock Control Register ...................................................................................................................... 62
Table 45:: Transmit Interface Control Register - E1 Mode .............................................................................................. 63
Table 46:: Transmit Interface Control Register - T1 Mode .............................................................................................. 64
Table 47:: Receive Interface Control Register (RICR) - E1 Mode ................................................................................... 66
Table 48:: Receive Interface Control Register (RICR) - T1 Mode ................................................................................... 67
Table 49:: DS1 Test Register .......................................................................................................................................... 68
Table 50:: Loopback Code Control Register .................................................................................................................... 69
Table 51:: Transmit Loopback Coder Register ................................................................................................................ 70
Table 52:: Receive Loopback Activation Code Register .................................................................................................. 70
Table 53:: Receive Loopback Deactivation Code Register ............................................................................................. 70
Table 54:: Transmit Sa Select Register ........................................................................................................................... 71
Table 55:: Transmit Sa Auto Control Register 1 .............................................................................................................. 71
Table 56:: Conditions on Receive side When TSACR1 bits Are enabled ........................................................................ 72
Table 57:: Transmit Sa Auto Control Register 2 .............................................................................................................. 72
Table 58:: Conditions on Receive side When TSACR1 bits enabled .............................................................................. 73
VIII
EXAR [ EXAR CORPORATION ]
