XRT86L30
SINGLE T1/E1/J1 FRAMER/LIU COMBO
13.0 PERFORMANCE MONITORING (PMON)
REV. 1.0.1
The function of Performance Monitoring is designed to accumulate error events like line code (bipolar)
violations, parity errors, frame alignment errors, etc. using saturating counters. When an accumulation interval
is signaled by a one-second interrupt (if enabled), the current counter value can be accessed by the
microprocessor. After a read by the microprocessor, the counters are reset and begin accumulating error
events for the next interval. The counters are reset in such a manner that error events during the reset period
are not missed.
13.1
Receive Line Code Violation Counter (16-Bit)
A line code violation is any event of pulses that does not comply with B8ZS or HDB3 encoding standards. Line
code violations and bi-polar violations cause the LCV counter to increment if this feature is enabled. The MSB
is stored in register 0x0900h and the LSB is stored in register 0x0901h.
13.2
16-Bit Receive Frame Alignment Error Counter (16-Bit)
A framing bit error event is defined as a error pattern found in FAS or bit 2 of the non-FAS. This counter is
disabled during loss of frame synchronization conditions. It is not disabled during loss of synchronization at
either the CAS or CRC-4 multiframe stage. The MSB is stored in register 0x0902h and the LSB is stored in
register 0x0903h.
13.3
Receive Severely Errored Frame Counter (8-Bit)
A severely errored frame event is defined as the occurrence of two consecutive errored frame alignment
signals that are not responsible for loss of frame alignment. The contents of this register are stored in
0x0904h.
13.4
Receive CRC-6/4 Block Error Counter (16-Bit)
A synchronization bit error event is defined as a CRC-6/4 error received. The counter is disabled during loss of
sync at either the Frame/FAS or ESF/CRC4 level, but it will not be disabled if loss of multiframe sync occurs at
the CAS level. The MSB is stored in register 0x0905h and the LSB is stored in register 0x0906h.
13.5
Receive Far-End Block Error Counter (16-Bit)
13.6
Receive Slip Counter (8-Bit)
A slip event is defined as a replication or deletion of a T1/E1 frame by the receiving slip buffer. The contents of
this register are stored in 0x0909h.
13.7
Receive Loss of Frame Counter (8-Bit)
A LOFC is a count of the number of times a Loss of FAS Frame has been declared. This parameter provides
the capability to measure an accumulation of short failure events. The contents of this register are stored in
0x090Ah.
13.8
Receive Change of Frame Alignment Counter (8-Bit)
A COFA is declared when the newly-locked framing is different from the one offered by off-line framer. The
contents of this register are stored in 0x090Bh.
13.9
Frame Check Sequence Error Counters 1, 2, and 3 (8-Bit Each)
These counters accumulate the times of occurrence the receive frame check sequence error is detected by the
LAPD controllers. The contents for LAPD 1 are stored in register 0x090Ch. The contents for LAPD 2 are
stored in register 0x091Ch. The contents for LAPD 3 are stored in register 0x092Ch.
13.10 PRBS Error Counter (16-Bit)
This counter contains the 16-bit PRBS bit error event. The MSB is stored in register 0x090Dh and the LSB is
stored in register 0x090Eh.
13.11 Transmit Slip Counter (8-Bit)
A slip event is defined as a replication or deletion of a T1/E1 frame by the transmit slip buffer. The contents of
this register are stored in 0x090Fh.
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EXAR [ EXAR CORPORATION ]
