XRT86L30
SINGLE T1/E1/J1 FRAMER/LIU COMBO
TRANSMIT SERIAL DATA INPUT
REV. 1.0.1
S
IGNAL
N
AME
P
IN
#
TYPE
DESCRIPTION
TxMSYNC/
TxINCLK
58
I/O Multiframe Sync Pulse/Transmit Input Clock
This pin is a multiplexed I/O pin. When the device is configured to be in standard
rate mode, this signal indicates the boundary of an outbound multi-frame. When
the device is configured to be in High-Speed mode, this pin functions as an input
clock signal for the high-speed Transmit back-plane interface.
DS1/E1 Standard Rate Mode (TxMSYNC as an Input)
This pin is configured to be an input if TxSERCLK is used as the timing reference
for the transmitter. TxMSYNC must pulse "High" for one period of TxSERCLK
when the transmit payload data Input Interface is processing the first bit of an out-
bound DS1/E1 multi frame.
NOTE: It is imperative that the TxMSYNC input signal be synchronized with the
TxSERCLK input signal.
DS1/E1 Standard Rate Mode (TxMSYNC as an output)
This pin is configured as an output if the recovered line clock or the MCLKIN input
pin is used as the timing reference for the transmitter. TxMSYNC will pulse "High"
for one period of TxSERCLK when the transmit payload data Input Interface is pro-
cessing the first bit of an outbound DS1/E1 frame.
DS1/E1 Non-Multiplexed High-Speed Backplane Interface
In the non-multiplexed high-speed interface mode, this pin is used as the timing
source for the high-speed data applied to TxSER. The non-multiplexed modes sup-
ported are MVIP 2.048MHz, 4.096MHz, and 8.192MHz.
NOTE: For DS1 mode, the DS-0 data is mapped into an E1 frame by ignoring every
fourth time slot (don’t care).
DS1/E1 Multiplexed High-Speed Backplane Interface
In the multiplexed high-speed interface mode, this pin is used as the timing source
for the high-speed data applied to TxSER. The multiplexed modes supported are
12.352MHz (DS1 only), 16.384MHz, 16.384MHz HMVIP, and 16.384MHz H.100.
For DS1 mode in 16.384MHz rate, the DS-0 data is mapped into an E1
frame by ignoring every fourth time slot (don’t care).
TxCHCLK
49
O
Transmit Channel Clock Output Signal
This pin indicates the boundary of each time slot of an outbound DS1/E1 frame.
DS1/E1 Mode
Each of these output pins is 192kHz/256kHz clock for DS1/E1 respectively which
pulses "High" whenever the Transmit Payload Data Input Interface block accepts
the LSB of each of the 24/32 time slots. The Terminal Equipment can use this clock
signal to sample the TxCHN0 through TxCHN4 time slot identifier pins.
DS1/E1 Fractional Interface Clock
In the fractional interface mode, TxCHCLK can be configured to function as one of
the following: The pin will output a gapped fractional clock that can be used by ter-
minal equipment input fractional payload data using the falling edge of the clock.
Otherwise the fractional payload data is clocked into the chip using the un-gapped
TxSERCLK pin.
9
EXAR [ EXAR CORPORATION ]
