xr
XRT83SL28
REV. 1.0.0
8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
RECEIVER SECTION
NAME
PIN
TYPE
DESCRIPTION
RTIP7
RTIP6
RTIP5
RTIP4
RTIP3
RTIP2
RTIP1
RTIP0
75
87
94
106
34
22
15
3
I
Receive Differential Tip Input
RTIP is the positive differential input from the line interface. Along with the
RRING signal, these pins should be coupled to a 1:1 transformer for proper
operation.
RRING7
RRING6
RRING5
RRING4
RRING3
RRING2
RRING1
RRING0
76
86
95
105
33
23
14
4
I
Receive Differential Ring Input
RRING is the negative differential input from the line interface. Along with the
RTIP signal, these pins should be coupled to a 1:1 transformer for proper oper-
ation.
TRANSMITTER SECTION
NAME
PIN
TYPE
DESCRIPTION
TxOE
9
I
Transmit Output Enable
Upon power up, the transmitters are tri-stated. Enabling the transmitters is
selected through the serial microprocessor interface by programming the
appropriate channel register if this pin is pulled "High". If the TxOE pin is
pulled "Low", all 8 transmitters are tri-stated.
NOTE: TxOE is ideal for redundancy applications. See the Redundancy
Applications Section of this datasheet for more details. Internally
pulled "Low" with a 50KΩ resistor.
DMO7
DMO6
DMO5
DMO4
DMO3
DMO2
DMO1
DMO0
73
72
O
Driver Monitor Output
When no transmit output pulse is detected for more than 128 TCLK cycles, the
DMO pin will go "High" for a minimum of one TCLK cycle. DMO will remain
"High" until the transmitter sends a valid pulse.
109
108
36
37
144
1
TCLK7
TCLK6
TCLK5
TCLK4
TCLK3
TCLK2
TCLK1
TCLK0
69
66
I
Transmit Clock Input
TCLK is the input facility clock used to sample the incoming TPOS/TNEG data.
TPOS/TNEG data can be sampled on either edge of TCLK selected by TCLK-
inv in the appropriate global register.
115
112
40
NOTE: TCLKinv is a global setting that applies to all 8 channels.
43
138
141
7
EXAR [ EXAR CORPORATION ]
