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XRT83SL28IV 参数 Datasheet PDF下载

XRT83SL28IV图片预览
型号: XRT83SL28IV
PDF下载: 下载PDF文件 查看货源
内容描述: 8路E1短程线路接口单元 [8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT]
分类和应用: 数字传输接口电信集成电路电信电路PC
文件页数/大小: 47 页 / 1000 K
品牌: EXAR [ EXAR CORPORATION ]
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XRT83SL28  
xr  
8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT  
REV. 1.0.0  
RECEIVER SECTION  
NAME  
PIN  
TYPE  
DESCRIPTION  
RLOS7  
RLOS6  
RLOS5  
RLOS4  
RLOS3  
RLOS2  
RLOS1  
RLOS0  
61  
65  
O
Receive Loss of Signal  
When a receive loss of signal occurs, the RLOS pin will go "High" for a mini-  
mum of one RCLK cycle. RLOS will remain "High" until the loss of signal con-  
dition clears. See the Receive Loss of Signal section of this datasheet for  
more details.  
116  
120  
48  
44  
137  
133  
RCLK7  
RCLK6  
RCLK5  
RCLK4  
RCLK3  
RCLK2  
RCLK1  
RCLK0  
58  
62  
O
O
O
Receive Clock Output  
RCLK is the recovered clock from the incoming data stream. If the incoming  
signal is absent, RCLK maintains its timing by using an internal master clock  
as its reference. RPOS/RNEG data can be updated on either edge of RCLK  
selected by RCLKinv in the appropriate global register.  
119  
123  
51  
NOTE: RCLKinv is a global setting that applies to all 8 channels.  
47  
134  
130  
RPOS7  
RPOS6  
RPOS5  
RPOS4  
RPOS3  
RPOS2  
RPOS1  
RPOS0  
59  
63  
RPOS/RDATA Output  
Receive digital output pin. In dual rail mode, this pin is the receive positive  
data output. In single rail mode, this pin is the receive non-return to zero (NRZ)  
data output.  
118  
122  
50  
46  
135  
131  
RNEG/LCV7  
RNEG/LCV6  
RNEG/LCV5  
RNEG/LCV4  
RNEG/LCV3  
RNEG/LCV2  
RNEG/LCV1  
RNEG/LCV0  
60  
64  
RNEG/LCV Output  
In dual rail mode, this pin is the receive negative data output. In single rail  
mode, this pin is a Line Code Violation indicator. If a line code violation or a bi-  
polar violation occur, the LCV pin will pull "High" for a minimum of one RCLK  
cycle. LCV will remain "High" until there are no more violations.  
117  
121  
49  
45  
136  
132  
6