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XRT83SL28
REV. 1.0.0
8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
1.5.1
RLOS (Receiver Loss of Signal)
The XRT83SL28 supports both G.775 or ETSI-300-233 RLOS detection scheme.
In G.775 mode, RLOS is declared when the received signal is less than 320mV for 32 consecutive pulse
periods (typical). The device clears RLOS when the receive signal achieves 12.5% ones density with no more
than 15 consecutive zeros in a 32 bit sliding window and the signal level exceeds 550mV (typical).
In ETSI-300-233 mode the device declares RLOS when the input level drops below 320mV (typical) for more
than 2048 pulse periods (1msec). The device exits RLOS when the input signal exceeds 550mV (typical) and
has transitions for more than 32 pulse periods with 12.5% ones density with no more than 15 consecutive
zero’s in a 32 bit sliding window. ETSI-300-233 RLOSS detection method is only available in Host mode.
1.5.2
AIS (Alarm Indication Signal)
The XRT83SL28 adheres to ITU-T G.775 or ETSI-300-233 specifications for an all ones pattern detection by
programming the appropriate channel register. The alarm indication signal is set to "1" if an all ones pattern is
detected. In G.775 mode, AIS is defined as 2 or less zeros in 2 consecutive double frame (512-bit window)
periods. AIS will clear when the incoming signal has 3 or more zeros in the same time period. In ETSI-300-233
mode, AIS is defined as less than 3 zeros in a 512-bit window. AIS detection scheme per ESTI-300-233 is only
available in Host mode.
1.5.3
LCV (Line Code Violation Detection)
In HDB3 mode, the LCV pin will be set to "High" if the receiver detects excessive zero’s, bipolar violations or
HDB3 code violations. If the device is configured in AMI mode, any bipolar violations will cause the LCV pin to
go "High".
1.6
Receive Jitter Attenuator
The jitter attenuator can be configured in the receive path to reduce phase and frequency jitter in the recovered
clock. The jitter attenuator uses a data FIFO (First In First Out) with a programmable depth of 32-bit or 64-bit. If
the LIU is used for line synchronization (loop timing systems), the JA should be enabled. When the Read and
Write pointers of the FIFO are within 2-Bits of over-flowing or under-flowing, the bandwidth of the jitter
attenuator is widened to track the short term input jitter, thereby avoiding data corruption. When this condition
occurs, the jitter attenuator will not attenuate input jitter until the Read/Write pointer’s position is outside the 2-
Bit window. The bandwidth is set to 2Hz when the JA is configured in the Receive or Transmit path. The JA has
a typical clock delay equal to ½ of the FIFO bit depth.
NOTE: If the LIU is used in a multiplexer/mapper application where stuffing bits are typically removed, the JA can be
configured in the transmit path to smooth out the gapped clock. See the Transmit Section of this datasheet.
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EXAR [ EXAR CORPORATION ]
