xr
XRT83SL28
REV. 1.0.0
8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
1.2
Peak Detector/Data Slicer
In the receive path, the line signal is coupled into the RTIP and RRing pins via a 1:1 transformer and are
converted into digital pulses by an adaptive data slicer. Clock and data signals are recovered from the output of
the slicer with the help of a digital PLL that provides excellent jitter accommodation for high input jitter
tolerance.
1.3
Clock and Data Recovery
The receive clock (RCLK) is recovered by the clock and data recovery circuitry. An internal PLL locks on the
incoming data stream and outputs a clock that’s in phase with the incoming signal. In the absence of an
incoming signal, RCLK maintains its timing by using MCLK as its reference. The recovered data can be
updated on either edge of RCLK. By default, data is updated on the rising edge of RCLK. To update data on
the falling edge of RCLK, set RCLKinv to "1" in the appropriate global register. Figure 6 is a timing diagram of
the receive data updated on the rising edge of RCLK. Figure 7 is a timing diagram of the receive data updated
on the falling edge of RCLK. The timing specifications are shown in Table 2.
FIGURE 6. RECEIVE DATA UPDATED ON THE RISING EDGE OF RCLK
RCLKR
RCLKF
RDY
RCLK
RPOS
or
RNEG
ROH
FIGURE 7. RECEIVE DATA UPDATED ON THE FALLING EDGE OF RCLK
RCLKF
RCLKR
RDY
RCLK
RPOS
or
RNEG
ROH
TABLE 2: TIMING SPECIFICATIONS FOR RCLK/RPOS/RNEG
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
RCLK Duty Cycle
RCDU
45
50
55
%
Receive Data Setup Time
Receive Data Hold Time
RCLK to Data Delay
RSU
RHO
RDY
150
150
-
-
-
-
-
-
ns
ns
ns
40
15
EXAR [ EXAR CORPORATION ]
