xr
XRT83SL28
REV. 1.0.0
8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
TABLE 3: TIMING SPECIFICATIONS FOR TCLK/TPOS/TNEG
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
TCLK Duty Cycle
TCDU
30
50
70
%
Transmit Data Setup Time
Transmit Data Hold Time
TCLK Rise Time (10% to 90%)
TCLK Fall Time (90% to 10%)
TSU
THO
50
30
-
-
-
-
-
-
ns
ns
ns
ns
-
TCLKR
TCLKF
40
40
-
NOTE: VDD=3.3V ±5%, TA=25°C, Unless Otherwise Specified
2.2
HDB3 Encoder
In single rail mode, the LIU can encode the TPOS input signal to AMI or HDB3 data. If HDB3 encoding is
selected, any sequence with four or more consecutive zeros in the input will be replaced with 000V or B00V,
where "B" indicates a pulse conforming to the bipolar rule and "V" representing a pulse violating the rule. An
example of HDB3 encoding is shown in Table 4.
TABLE 4: EXAMPLES OF HDB3 ENCODING
NUMBER OF PULSES BEFORE
NEXT 4 ZEROS
Input
0000
000V
B00V
HDB3 (Case 1)
HDB3 (Case 2)
Odd
Even
2.3
Transmit Jitter Attenuator
The XRT83SL28 LIU is ideal for multiplexer or mapper applications where the network data crosses multiple
timing domains. As the higher data rates are de-multiplexed to E1 data, stuffing bits are typically removed
which can leave gaps in the incoming data stream. The JA can be configured in the transmit path with a 32-Bit
or 64-Bit FIFO that is used to smooth the gapped clock into a steady E1 output. The maximum gap width the
JA in the Transmit path can tolerate is shown in Table 5.
TABLE 5: MAXIMUM GAP WIDTH FOR MULTIPLEXER/MAPPER APPLICATIONS
FIFO DEPTH
32-Bit
MAXIMUM GAP WIDTH
20 UI
50 UI
64-Bit
NOTE: If the LIU is used in a loop timing system, the JA should be configured in the receive path. See the Receive Section
of this datasheet.
21
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