XRT83SL28
xr
8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.0
2.0 TRANSMIT PATH LINE INTERFACE
The transmit path of the XRT83SL28 LIU consists of 8 independent E1 transmitters. The following section
describes the complete transmit path from TCLK/TPOS/TNEG inputs to TTIP/TRING outputs. A simplified
block diagram of the transmit path is shown in Figure 12.
FIGURE 12. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT PATH
TTIP
TCLK
TPOS
TNEG
HDB3
Encoder
Tx Jitter
Attenuator
Timing
Control
Tx Pulse Shaper
Line Driver
TRING
2.1
TCLK/TPOS/TNEG Digital Inputs
In dual rail mode, TPOS and TNEG are the digital inputs for the transmit path. In single rail mode, TNEG can
be tied to ground unless Hardware mode is selected (see the Hardware Pin Description). The XRT83SL28 can
be programmed to sample the inputs on either edge of TCLK. By default, data is sampled on the falling edge of
TCLK. To sample data on the rising edge of TCLK, set TCLKinv to "1" in the appropriate global register.
Figure 13 is a timing diagram of the transmit input data sampled on the falling edge of TCLK. Figure 14 is a
timing diagram of the transmit input data sampled on the rising edge of TCLK. The timing specifications are
shown in Table 3.
FIGURE 13. TRANSMIT DATA SAMPLED ON FALLING EDGE OF TCLK
TCLKR
TCLKF
TCLK
TPOS
or
TNEG
TSU
THO
FIGURE 14. TRANSMIT DATA SAMPLED ON RISING EDGE OF TCLK
TCLKF
TCLKR
TCLK
TPOS
or
TNEG
TSU
THO
20
EXAR [ EXAR CORPORATION ]
