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MP8830 参数 Datasheet PDF下载

MP8830图片预览
型号: MP8830
PDF下载: 下载PDF文件 查看货源
内容描述: 三路10位高速模拟数字转换器,具有数字控制的参考 [Triple 10-bit High Speed Analog-to-Digital Converter with Digitally Controlled References]
分类和应用: 转换器
文件页数/大小: 20 页 / 291 K
品牌: EXAR [ EXAR CORPORATION ]
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MP8830  
Parameter  
Symbol  
Min  
Typ  
Max Units  
Test Conditions/Comments  
3-State Leakage  
I
–10  
10 µA  
In pass-through mode  
OZ  
Digital Timing Specifications2  
For testing, rise time = fall time =  
10 ns. Output loading = 60 pF except for  
AD0-AD9 for which loading is 40 pF. Rise  
and fall times faster than 5 ns should be  
avoided.  
AENL, BENL, CENL  
Pulse Width  
t
1
125  
ns  
D/A Data Hold Time  
t
t
20  
ns  
ns  
2
BENL Rising Edge to CENL Rising  
Edge  
270  
3
AENL Rising Edge to CVL Falling  
Edge  
t
4
30  
ns  
D/A Data Setup Time  
t
t
20  
20  
ns  
ns  
5
Analog Input Hold Time  
Measured as part of analog feedthrough test.  
6
Note, t  
< t  
+ t  
tapmax  
4min 6min.  
CVL Rising Edge to AENL Rising  
Edge  
t
t
230  
ns  
7
A/D Data Enable Time  
40 ns  
CVL to Channel A data.  
BENL to Channel B data.  
CENL to Channel C data.  
8
CENL Rising Edge to CVL Rising  
Edge  
t
t
40  
50  
20  
ns  
ns  
9
Analog Input Settled to 0.1%  
Assumes the sample is taken at the rising  
edge of AENL.  
10  
A/D Data Hold Time  
Aperture Delay  
t
t
ns  
11  
20  
40 ns  
Analog sampling window delay from CVL ris-  
ing () edge (start) or AENL rising () edge  
(end).  
AP  
CVL Falling Edge to BENL Rising  
Edge  
t
12  
t
13  
t
14  
t
15  
t
16  
t
17  
180  
ns  
50 ns  
50 ns  
40 ns  
40 ns  
40 ns  
Delay from CD5-14 to AD0-9 with  
CREN=1  
Delay from AD0-9 to CD5-14 with  
CREN = 1  
Delay from DCL Falling Edge to  
Clamp on.  
External analog clamp voltage settling de-  
pends on external circuitry.  
Delay from DCL Rising Edge to  
Clamp off.  
External analog clamp voltage settling de-  
pends on external circuitry.  
Time for AD0-9 and CD5-14 to switch  
from normal operation to pass  
through mode or vise versa (i.e. bus  
contention).  
0
User should stop driving the bus before  
changing the mode and data will not be valid  
for 40 ns after a change of mode.  
Digital Quiet Time  
t
15  
ns  
ns  
This quiet time is necessary to reduce digital  
crosstalk during the critical sampling time.  
The accuracy of each conversion may be cor-  
rupted due to digital noise on the board during  
this period.  
18  
19  
Digital Quiet Time  
t
40  
This quiet time is necessary to reduce digital  
crosstalk during the critical sampling time.  
The accuracy of each conversion may be cor-  
rupted due to digital noise on the board during  
this period.  
Notes  
1
Production testing performanced at 25°C.  
2
Not production tested.  
Rev. 1.00  
6
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