MP8830
PIN OUT DEFINITIONS
PIN NO.
NAME
DV
DESCRIPTION
PIN NO.
NAME
DESCRIPTION
1
Digital Positive Power Supply
DAC Input Pin 14
DAC Input Pin 13
DAC Input Pin 12
DAC Input Pin 11
DAC Input Pin 10
DAC Input Pin 9
33
ASENS
Sensing Voltage for Biasing the
DD
A Channel
2
CD14
CD13
CD12
CD11
CD10
CD9
CD8
CD7
CD6
CD5
CD4
CD3
CD2
CD1
CD0
34
AFORC
Forcing Voltage for Biasing the
A Channel
3
4
35
36
37
38
39
40
41
AAN
A Channel Analog Input
Analog Negative Power Supply
Clamp Voltage A
5
AGND1
ACLP
VCAL
VINMX
DGND
DCL
6
7
Calibration Input Voltage
Analog Mux Control
8
DAC Input Pin 8
9
DAC Input Pin 7
Digital Negative Power Supply
10
11
12
13
14
15
16
17
18
DAC Input Pin 6
Black Level Clamp Control
(Active Low)
DAC Input Pin 5
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
N/C
No Connection
DAC Input Pin 4
DGND
Digital Negative Power Supply
Digital Positive Power Supply
FAST Mode Enable
DAC Input Pin 3
DV
DAC Input Pin 2
DD
FAST
DAC Input Pin 1
GND3
Analog Negative Power Supply
Analog Positive Power Supply
Pass Through Mode Enable
READ not WRITE
DAC Input Pin 0
V
DD3
CV
Analog Positive Power Supply
DD
CREN
RNW
CENL
BENL
AENL
CVL
CSENS
Sensing Voltage for Biasing the
C Channel
19
CFORC
Forcing Voltage for Biasing the
C Channel
Channel C Data Clock
Channel B Data Clock
Channel A Data Clock
Cycle Clock
20
21
CAN
C Channel Analog Input
CGND2
Analog Ground Related to
DAC Bias
22
23
24
25
CCLP
Clamp Voltage C
AD9
ADC Data Output 9
CGND1
Analog Negative Power Supply
Analog Positive Power Supply
AD8
ADC Data Output 8
BV
AD7
ADC Data Output 7
DD
BSENS
Sensing Voltage for Biasing the
B Channel
AD6
ADC Data Output 6
AD5
ADC Data Output 5
26
BFORC
Forcing Voltage for Biasing the
B Channel
AD4
ADC Data Output 4
AD3
ADC Data Output 3
27
28
BAN
B Channel Analog Input
AD2
ADC Data Output 2
BGND2
Analog Ground Related to
DAC Bias
AD1
ADC Data Output 1
29
30
31
32
BCLP
Clamp Voltage B
AD0
ADC Data Output 0
BGND1
Analog Negative Power Supply
Analog Positive Power Supply
DGND
Digital Negative Power Supply
AV
DD
AGND2
Analog Ground Related to
DAC Bias
Note: All digital signals are active high unless otherwise noted.
Rev. 1.00
3