MP8830
ELECTRICAL CHARACTERISTICS
Unless otherwise specified: AVDD = DVDD= 5 V, DGND = AGND = 0 V, VREF = AVDD ꢀ 0.2
Temperature = 0 to 60°C1
A/D Converters
Parameter
Symbol
N
Min
10
Typ
Max Units
Test Conditions/Comments
Resolution
Bits
Differential Non-Linearity
DNL
–1
ꢁ0.75
ꢁ0.5
2
2
2
LSB
Gain DAC = 000 (hex), offset DAC = 00 (hex).
Monotonicity guaranteed.
Differential Non-Linearity
Integral Non-Linearity
Integral Non-Linearity
Zero Scale Error
DNL
INL
–1
LSB
Gain DAC = 1FF (hex), offset DAC = 00 (hex).
Monotonicity guaranteed.
2.75 LSB
Gain DAC = 000 (hex), offset DAC = 00 (hex),
Best fit straight line.
INL
1.5
2
9
LSB
mV
Gain DAC = 1FF (hex), offset DAC = 00 (hex),
Best fit straight line.
ZSE
–15
Measured with offset and gain DACs set to
000. Offset is defined as the difference be-
tween the clamp voltage and the analog input
voltage which results in the transition of the
ADC code from 004 to 005.
2
Zero Scale Drift
ZSD
50
µV/°C
Measured as the change in the ZSE over tem-
perature. This error does not include the error
introduced by the external V
amplifier or
REF
external V
resistor divider.
REF
DC Input Range
A
IN
VCLP
–5mV
2.92 V +
VCLP
V
The digitizing range is set with the Gain DAC
and offset DAC. Please note A (min) is
IN
–5 mV
VCLP – 4 LSB = V and A (max) is GFS
(max) + ZSR (max) + VCLP – 4 LSB.
RB IN
Data Rate
FS
1.25
0
MSPS
V
The conversion rate is determined by the tim-
ing diagram and timing specifications. Set by
the CVL period.
Analog Input Voltage Change from
Sample to Sample
DA
ꢁFS
Assuming A voltage remains within the spe-
IN
IN
2
cified digitizing range based on the offset and
gain DAC codes.
2
Input Capacitance
C
45 pF
Measured with A DC = 2.5 V and AENL =
IN
IN
low.
Gain DAC
Resolution
N
9
Bits
Differential Non-Linearity
Integral Non-Linearity
Gain DAC Full Scale
DNL
INL
–1
+2.25 LSB
+2 LSB
GFS
2.6
2.68
1.26
2.76
V
Gain DAC = 1FF
(V – V
)
V
RT
is the top of the ADC reference ladder.
RT
RB
Refer to block diagram.
Gain DAC Zero Scale
(V – V
GZS
1.22
1.3
V
Gain DAC = 000
)
V
RB
is the bottom of the ADC reference lad-
RT
RB
der. Refer to block diagram.
2
Maximum Gain Change per Cycle
MGC
50 % FSR After the specified maximum change in gain
DAC setting, the ADC should output the same
code ꢁ1 LSB for all of the following conver-
sions assuming the analog input remains
fixed, i.e. DC.
2
Settling Time (MGC)
ts-gd
200
ns
Rev. 1.00
4
EXAR [ EXAR CORPORATION ]
