Table 9-4. 4450 pin list (by signal name) - second half
Ball # Signal Name Ball # Signal Name Ball # Signal Name Ball # Signal Name Ball # Signal Name
U5
N7
V5
n1_bus1[0]
n1_bus1[1]
n1_bus1[2]
n1_bus1[3]
n1_clk_0
M2
T10
J3
vdda_pll
E1
vddr
vddr
vddr
vddr
vddr
vddr
vddr
vddr
vddr
vddr
vddr
vdds
vdds
vdds
vdds
vref_ddr[0]
vref_ddr[1]
vref_ddr[2]
vref_host
vref_netw
vss
C12
L14
R18
N18
K11
K18
H10
E11
A10
C9
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vssa_ddr_pll
N10
G6
vtth_serdes
we_n
vdda_serdes
D10
D13
D16
C4
vdde
vdde
vddh
V6
M3
R15
V3
U6
V2
n1_clk_1
M17 vddh
M15 vddh
D7
n1_ctrl_0
F12
F3
V4
n1_ctrl_1
P17
U17
J15
J17
F15
vddh
vddh
vddh
vddh
vddh
N9
P9
n1_bus1_n
n1_bus1_p
n1_bus0_n
n1_bus0_p
net_config[0]
net_config[1]
F6
F9
V9
H5
A7
U9
K3
T8
H9
M11 vddi
T9
E8
K2
L12
J12
H12
G11
G10
G9
vddi
vddi
vddi
vddi
vddi
vddi
vddi
vddi
vddi
vddi
vddi
vddi
T11
T12
B18
A11
A6
C6
A5
odt
A4
M5
M7
K4
pll_bypass
pll_mode[1]
por_n
H8
J9
A1
M4
H2
V14
T13
U14
V15
U15
T14
R13
U13
A2
prefclk
L18
T1
B3
ras_n
G8
E5
rmii_bus0[0]
rmii_bus0[1]
rmii_bus0[2]
rmii_bus1[0]
rmii_bus1[1]
rmii_bus1[2]
J8
G18
J11
B17
J10
H11
E14
A18
C15
R10
R11
L10
V13
R12
K10
L11
V18
D2
G3
H1
K8
vss
L8
vss
M8
M9
vss
L2
vss
R2
M10 vddi
vss
K9
rmii_ref_clk
rmii_vdd
R4
vddn
vddn
vddn
vddn
vddn
vddr
vddr
vddr
vddr
vddr
vddr
vddr
vss
V1
T6
vss
R6
sdclk_diff_n
sdclk_diff_p
sdclk_fb_i
sdclk_fb_o
serdes_rref
srefclk_n
U2
vss
L9
A3
V7
vss
U7
C1
P7
vss
R8
B1
B11
B14
B2
vss
R9
U10
T7
vss
V10
P14
H14
E3
vss
R7
srefclk_p
F17
B5
vss
N6
L5
testmode
vss
vdd_reserved
vdda_ddr_pll
B8
M12 vss
A13 vss
N2
vssa_pll
D3
C18
P10
vttn_serdes
4450 – Data Sheet, DS-0131-06
Page85
Hifn Confidential
EXAR [ EXAR CORPORATION ]
