I Document Changes/Revisions
Documentation Changes include additions, deletions, and modifications made to this
document. This section identifies the changes made in each release of the document.
I.1 Document Revision A
Initial Release.
I.2 Document Revision B
Update 1.
Update 2.
Acronym Section: Deleted duplicate acronyms, added TLS.
Chapter 1: Slight revision and clean-up. Changed SA support from 300 to
250.
Update 3.
Chapter 2: Minor editorial revisions. Changed SA support from 300 to 250
in Section 2.2.
Update 4.
Update 5.
Chapter 3 Section 3.1: Changed IPSec Performance from 2.1 to 2.0.
Chapter 4: Slight revision and clean-up. Added details on Post Crypto
Processor to Table 5. Section 4.4 updated to more accurately reflect clock
domains.
Update 6.
Update 7.
Chapter 5: Minor editorial revisions.
Chapter 6: Major update. Added connection diagrams for each GMAC and
SDRAM interface. Updated details on GPIO functionality and pin usage.
Update 8.
Update 9.
Chapter 7: Major update. Modified DC Characteristics for each interface,
GMAC, SDRAM, GPIO.
Chapter 9: Modified a[13] to a[13]\cke and ba[2] to ba[2]\cke.
I.3 Document Revision C
Update 1.
All sections: removed references to optional DDR memory.
Update 2.
Update 3.
Section 4.1 Chip Architecture: replaced Block Diagram.
Section 6.2.1.2 Connection drawings: added signal names to Host Side and
moved hx_clk_0.
Update 4.
Update 5.
Section 6.5 PLL Interface, Table 21: Description for pll_ref_clk added “or
125MHz ref clock”; pll_mode[1] now only selects between the 25 and
125MHz input ref clock.
Section 6.7 General Purpose Pins, Table 22: changed reset function of
dpu_gpio[4] and dpu_gpio[3] to ddr_config1 and ddr_config0. DDR
Configuration section rewritten to reflect changes in DDR memory. Added
Table 24 DDR2 Memory Configuration Sizing.
Update 6.
Update 7.
Section 6.9 Power and Ground Pins: removed 2.5V(DDR1) from vddr; added
vdds, corrected vref_ddr[2:0] to 0.9V for DDR2; added description for
vttn_serdes and vtth_serdes; deleted vdda_srefbuf.
Section 7.5 Power Sequencing: added second paragraph further describing
the required power sequence.
4450 – Data Sheet, DS-0131-06
Page88
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