Table 8-2. 125 MHz PLL_REF Clock
Number
Description
Min
Nominal
Max
Units
MHz
ns
1
2
3
4
Clock frequency
125
Clock width high
Clock width low
3.6
3.6
ns
Clock rise time from VIL to VIH
2
2
ns
5
Clock fall time from VIH to VIL
ns
n/a
n/a
n/a
Duty cycle
45
55
200
4
%
Jitter (peak to peak)
PLL lock time
ps
µsec
(500 reference clock cycles)
Table 8-3. 25 MHz PLL_REF Clock
Number
Description
Min
Nominal
Max
Units
MHz
ns
1
2
3
4
Clock frequency
25
Clock width high
Clock width low
18
18
ns
Clock rise time from VIL to VIH
4
4
ns
5
Clock fall time from VIH to VIL
ns
n/a
n/a
n/a
Duty cycle
45
55
%
Jitter (peak to peak)
PLL lock time
200
20
ps
µsec
(500 reference clock cycles)
8.3 RMII Timing
The 4450 supports the 802.3-2002 standard specifications. With a PLL_REF_CLK input of
25MHz, this port supports 100 Mbps fast Ethernet RMII timing.
The only interface difference between RMII PHY and RMII MAC mode is the direction of the
clock pin. In MAC mode, the clock is an output, and in PHY mode the clock is an input.
Table 8-4. RMII Timing
Mode
TXD
RXD
Setup
Hold
Setup
Hold
PHY
2.00 ns
2.00 ns
2.00 ns
2.00 ns
4.50 ns
4.50 ns
2.50 ns
2.50 ns
MAC
4450 – Data Sheet, DS-0131-06
Page72
Hifn Confidential
EXAR [ EXAR CORPORATION ]
