sure that there are no reverse-bias conditions during the power-on process that could cause
improper operation or possible damage to the 44x0/84x0 chip. A minimum delay of 1ms
should be allowed between the bring-up of each supply. To minimize potential bus conflicts,
a maximum delay of 500ms for the complete power-up sequence should be adhered to.
Please refer to the 4450/8450 Hardware Design Application Note (AN-0145) for more
detailed information.
4450 – Data Sheet, DS-0131-06
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