EtronTech
EM68C16CWQG
Figure 10. OCD adjust mode
OCD calibration mode exit
OCD adjust mode
EMRS
EMRS
NOP
NOP
NOP
NOP
NOP
NOP
CMD
CK#
CK
WL
WR
DQS#
DQS_in
tDS tDH
DT0
VIH(dc)
VIH(ac)
DQ_in
DM
DT1
DT2
DT3
VIL(ac)
VIL(dc)
NOTE 1: For proper operation of adjust mode, WL = RL - 1 = AL + CL - 1tCK and tDS /tDH should be met as shown in the figure.
NOTE 2: For input data pattern for adjustment, DT0-DT3 is a fixed order and is not affected by burst type
(i.e., sequential or interleave)
Figure 11. ODT update delay timing-tMOD
NOP
EMRS
NOP
NOP
NOP
NOP
CMD
CK#
CK
ODT
tIS
tMOD, max
Updating
tAOFD
tMOD, min
Rtt
Old setting
New setting
NOTE 1: To prevent any impedance glitch on the channel, the following conditions must be met:
- tAOFD must be met before issuing the EMRS command.
- ODT must remain LOW for the entire duration of tMOD window, until tMOD, max is met.
then the ODT is ready for normal operation with the new setting, and the ODT signal may be raised again to turned
on the ODT.
NOTE 2: EMRS command directed to EMR(1), which updates the information in EMR(1)[A6,A2], i.e. Rtt (Nominal).
NOTE 3: "setting" in this diagram is the Register and I/O setting, not what is measured from outside.
Rev. 1.2
35
Apr. /2016
ETRON [ ETRON TECHNOLOGY, INC. ]
