EtronTech
EM68C16CWQG
NOTE 38: When the device is operated with input clock jitter, this parameter needs to be derated by the actual
tERR(6-10per) of the input clock. (output deratings are relative to the SDRAM input clock.)
NOTE 39: When the device is operated with input clock jitter, this parameter needs to be derated by the actual
tJIT(per) of the input clock. (output deratings are relative to the SDRAM input clock.)
NOTE 40: When the device is operated with input clock jitter, this parameter needs to be derated by the actual
tJIT(duty) of the input clock. (output deratings are relative to the SDRAM input clock.)
NOTE 41: When the device is operated with input clock jitter, this parameter needs to be derated by { -
tJIT(duty),max - tERR(6-10per),max } and { - tJIT(duty),min - tERR(6-10per),min } of the actual input clock.
(output deratings are relative to the SDRAM input clock.)
NOTE 42: For tAOFD of DDR2-667/800/1066, the 1/2 clock of tCK in the 2.5 x tCK assumes a tCH(avg), average input
clock HIGH pulse width of 0.5 relative to tCK(avg). tAOF,min and tAOF,max should each be derated by the
same amount as the actual amount of tCH(avg) offset present at the DRAM input with respect to 0.5.
NOTE 43: If refresh timing is violated, data corruption may occur and the data must be re-writtern with valid data
before a valid READ can be executed.
NOTE 44: This is an optional feature. For detailed information, please refer to “operating temperature condition”.
Rev. 1.2
33
Apr. /2016
ETRON [ ETRON TECHNOLOGY, INC. ]
