EtronTech
EM68C16CWQG
Timing Waveforms
Figure 8. Initialization sequence after power-up
tCH tCL
tIS
CK
CK#
CKE
ODT
tIS
EMR
S
ANY
CMD
EMR
S
EMR
S
PRE
ALL
PRE
ALL
REF
REF
MRS
NOP
MRS
Command
Follow OCD Flowchart
tRFC
400ns
tRP
tMRD
tMRD
tRP
tRFC
tMRD
tOIT
OCD
OCD
Default
DLL
ENABLE
DLL
RESET
CAL.MOD
E EXIT
min 200 Cycle
NOTE 1: To guarantee ODT off, VREF must be valid and a LOW level must be applied to the ODT pin.
Figure 9. OCD drive mode
OCD calibration mode exit
EMRS
Enter Drive mode
EMRS
NOP
NOP
NOP
CMD
CK#
CK
Hi-Z
Hi-Z
DQS
DQS HIGH & DQS# LOW for Drive(1), DQS LOW & DQS# HIGH for Drive(0)
DQS#
DQs HIGH for Drive(1)
DQs LOW for Drive(0)
DQ
tOIT
tOIT
NOTE : Drive mode, both Drive(1) and Drive(0), is used for controllers to measure DDR2 SDRAM Driver
impedance.In this mode, all outputs are driven out tOIT after "enter drive mode" command and all output
drivers are turned-off tOIT after "OCD calibration mode exit" command.
Rev. 1.2
34
Apr. /2016
ETRON [ ETRON TECHNOLOGY, INC. ]
