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EM68C16CWQG-18IH 参数 Datasheet PDF下载

EM68C16CWQG-18IH图片预览
型号: EM68C16CWQG-18IH
PDF下载: 下载PDF文件 查看货源
内容描述: [64M x 16 bit DDRII Synchronous DRAM (SDRAM)]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 60 页 / 1276 K
品牌: ETRON [ ETRON TECHNOLOGY, INC. ]
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EtronTech  
EM68C16CWQG  
Table 30. Input clock jitter spec parameter  
-18I  
-25I  
-3I  
Parameter  
Clock period jitter  
Symbol  
Unit Note  
Min. Max. Min. Max. Min. Max.  
tJIT (per)  
tJIT (per,lck)  
tJIT (cc)  
-90  
-80  
90 -100 100 -125 125  
80 -80 80 -100 100  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
33  
33  
33  
33  
33  
33  
33  
33  
33  
33  
33  
Clock period jitter during DLL locking  
period  
Cycle to cycle clock period jitter  
-180 180 -200 200 -250 250  
-160 160 -160 160 -200 200  
-132 132 -150 150 -175 175  
-157 157 -175 175 -225 225  
-175 175 -200 200 -250 250  
-188 188 -200 200 -250 250  
Cycle to cycle clock period jitter during DLL  
locking period  
Cumulative error across 2 cycles  
tJIT (cc,lck)  
tERR (2per)  
tERR (3per)  
tERR (4per)  
tERR (5per)  
Cumulative error across 3 cycles  
Cumulative error across 4 cycles  
Cumulative error across 5 cycles  
Cumulative error across n cycles, n=6...10,  
inclusive  
Cumulative error across n cycles,  
n=11...50, inclusive  
tERR (6-10per) -250 250 -300 300 -350 350  
tERR (11-50per) -425 425 -450 450 -450 450  
Duty cycle jitter  
tJIT (duty)  
-75  
75 -100 100 -125 125  
NOTE 34: These parameters are specified per their average values, however it is understood that the following  
relationship between the average timing and the absolute instantaneous timing holds at all times. (Min  
andmax of SPEC values are to be used for calculations in the table below.)  
Table 31. Absolute clock period average values  
Parameter  
Symbol  
Min.  
Max.  
Unit  
Absolute clock period  
tCK (abs)  
tCK(avg),min + tJIT(per),min  
tCK(avg),max + tJIT(per),max  
ps  
Absolute clock HIGH pulse width  
Absolute clock LOW pulse width  
tCH (abs)  
tCL (abs)  
tCH(avg),min * tCK(avg),min + tCH(avg),max * tCK(avg),max + ps  
tJIT(duty),min tJIT(duty),max  
tCL(avg),min * tCK(avg),min + tCL(avg), max * tCK(avg),max + ps  
tJIT(duty),min tJIT(duty), max  
NOTE 35: tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not  
an input specification parameter. It is used in conjunction with tQHS to derive the DRAM output timing tQH  
The value to be used for tQH calculation is determined by the following equation;  
.
tHP = Min ( tCH(abs), tCL(abs) ),  
where,  
tCH(abs) is the minimum of the actual instantaneous clock HIGH time;  
tCL(abs) is the minimum of the actual instantaneous clock LOW time;  
NOTE 36: tQHS accounts for:  
1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the  
input is transferred to the output; and  
2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next  
transition, both of which are independent of each other, due to data pin skew, output pattern effects,  
and p-channel to n-channel variation of the output drivers  
NOTE 37: tQH = tHP tQHS, where: tHP is the minimum of the absolute half period of the actual input clock; and tQHS is  
the specification value under the max column. {The less half-pulse width distortion present, the larger the  
tQH value is; and the larger the valid data eye will be.}  
Rev. 1.2  
32  
Apr. /2016  
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