EtronTech
EM68C16CWQG
Table 26. IDD specification parameters and test conditions
(VDD = 1.8V 0.1V, TOPER = -40~95 C)
-18I
-25I
Max.
-3I
Parameter & Test Condition
Symbol
Unit
Operating one bank active-precharge current:
tCK =tCK (min), tRC = tRC (min), tRAS = tRAS(min); CKE is HIGH, CS# is HIGH
between valid commands; Address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
Operating one bank active-read-precharge current:
IOUT = 0mA; BL = 4, CL = CL (min), AL = 0; tCK = tCK (min),tRC = tRC (min), tRAS
= tRAS(min), tRCD = tRCD (min);CKE is HIGH, CS# is HIGH between valid
commands;Address bus inputs are switching; Data pattern is same as IDD4W
Precharge power-down current:
IDD0
70
65
75
60
mA
IDD1
80
70
mA
IDD2P
IDD2Q
IDD2N
10
35
35
10
35
35
10
35
35
mA
mA
mA
All banks idle;tCK =tCK (min); CKE is LOW; Other control and address bus
inputs are STABLE; Data bus inputs are FLOATING
Precharge quiet standby current:
All banks idle; tCK =tCK (min); CKE is HIGH, CS# is HIGH; Other control
and address bus inputs are STABLE; Data bus inputs are FLOATING
Precharge standby current:
All banks idle; tCK = tCK (min); CKE is HIGH, CS# is HIGH; Other control and
address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Active power-down current:
All banks open; tCK =tCK (min); CKE is LOW; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING
MRS(A12)=0
MRS(A12)=1
25
20
25
20
25
20
mA
mA
IDD3P
Active standby current:
All banks open; tCK = tCK(min), tRAS = tRAS (max), tRP = tRP (min); CKE is
HIGH, CS# is HIGH between valid commands; Other control and address
bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating burst write current:
All banks open,continuous burst writes; BL = 4, CL = CL (min), AL = 0;
tCK= tCK (min), tRAS = tRAS (max), tRP = tRP (min); CKE is HIGH, CS# is HIGH
between valid commands; Address bus inputs are switching; Data bus
inputs are switching
IDD3N
50
45
40
95
mA
mA
IDD4W
125
105
Operating burst read current:
All banks open, continuous burst reads, IOUT = 0mA; BL = 4, CL = CL
(min), AL = 0; tCK = tCK (min), tRAS = tRAS (max), tRP = tRP (min); CKE is
HIGH, CS# is HIGH between valid commands; Address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
IDD4R
115
95
85
mA
Burst refresh current:
tCK = tCK (min); refresh command at every tRFC (min) interval; CKE is HIGH,
CS# is HIGH between valid commands; Other control and address bus
inputs are SWITCHING; Data bus inputs are SWITCHING
Self refresh current:
CK and CK# at 0V; CKE ≤ 0.2V;Other control and address bus inputs are
FLOATING; Data bus inputs are FLOATING
IDD5
105
10
100
10
95
10
mA
mA
IDD6
Operating bank interleave read current:
All bank interleaving reads, IOUT= 0mA; BL = 4, CL = CL (min), AL =tRCD
IDD7
185
170
155 mA
(min) - 1 x tCK (min); tCK = tCK (min), tRC = tRC (min), tRRD = tRRD (min), tRCD
=
tRCD (min); CKE is HIGH, CS# is HIGH between valid commands; Address
bus inputs are STABLE during DESELECTs.Data pattern is same as IDD4R
NOTE 1: IDD specifications are tested after the device is properly initialized.
NOTE 2: Input slew rate is specified by AC Parametric Test Condition.
NOTE 3: IDD parameters are specified with ODT disabled.
NOTE 4: Data bus consists of DQ, DM, LDQS, LDQS#, UDQS and UDQS#. IDD values must be met with all combinations of EMRS bits
10 and 11.
NOTE 5: LOW = VIN ≦ VILAC(max), HIGH = VIN ≧ VIHAC(min), STABLE = inputs stable at a HIGH or LOW level, FLOATING = inputs at
VREF = VDDQ/2, SWITCHING = inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for
address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ
signals not including masks or strobes.
Rev. 1.2
25
Apr. /2016
ETRON [ ETRON TECHNOLOGY, INC. ]
