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EM68C08CWAE-3H 参数 Datasheet PDF下载

EM68C08CWAE-3H图片预览
型号: EM68C08CWAE-3H
PDF下载: 下载PDF文件 查看货源
内容描述: [128M x 8 bit DDRII Synchronous DRAM (SDRAM)]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 63 页 / 512 K
品牌: ETRON [ ETRON TECHNOLOGY, INC. ]
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EtronTech  
EM68C08CWAE  
Figure 11. ODT update delay timing-tMOD  
EMRS  
NOP  
NOP  
NOP  
NOP  
NOP  
CMD  
CK#  
CK  
ODT  
tIS  
tMOD, max  
Updating  
tAOFD  
tMOD, min  
Rtt  
Old setting  
New setting  
NOTE 1: To prevent any impedance glitch on the channel, the following conditions must be met:  
- tAOFD must be met before issuing the EMRS command.  
- ODT must remain LOW for the entire duration of tMOD window, until tMOD, max is met.  
then the ODT is ready for normal operation with the new setting, and the ODT signal may be raised again to turned  
on the ODT.  
NOTE 2: EMRS command directed to EMR(1), which updates the information in EMR(1)[A6,A2], i.e. Rtt (Nominal).  
NOTE 3: "setting" in this diagram is the Register and I/O setting, not what is measured from outside.  
Figure 12. ODT update delay timing-tMOD, as measured from outside  
CK#  
CK  
EMRS  
NOP  
NOP  
NOP  
NOP  
NOP  
CMD  
ODT  
tIS  
tAOND  
tAOFD  
tMOD, max  
Rtt  
Old setting  
New setting  
NOTE 1: EMRS command directed to EMR(1), which updates the information in EMR(1)[A6,A2], i.e. Rtt (Nominal).  
NOTE 2: "setting" in this diagram is measured from outside.  
Rev. 1.3  
38  
Oct. /2015  
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