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EM68C08CWAE-3H 参数 Datasheet PDF下载

EM68C08CWAE-3H图片预览
型号: EM68C08CWAE-3H
PDF下载: 下载PDF文件 查看货源
内容描述: [128M x 8 bit DDRII Synchronous DRAM (SDRAM)]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 63 页 / 512 K
品牌: ETRON [ ETRON TECHNOLOGY, INC. ]
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EtronTech  
EM68C08CWAE  
Figure 16. ODT timing mode switch at exit power-down mode  
T0  
T1  
T4  
T5  
T6  
T7  
T8  
T9  
T10  
T11  
CK#  
CK  
tAXPD  
tIS  
VIH(ac)  
CKE  
Exiting from Slow Active Power Down Mode or Precharge power Down Mode.  
tIS  
ODT  
VIL(ac)  
Active & Standby mode  
tAOFD  
timings to be applied.  
Internal  
Term Res.  
RTT  
tIS  
ODT  
Power Down mode  
VIL(ac)  
timings to be applied.  
tAOFPD max  
Internal  
Term Res.  
RTT  
tIS  
VIH(ac)  
Active & Standby mode  
ODT  
timings to be applied.  
tAOND  
RTT  
Internal  
Term Res.  
tIS  
VIH(ac)  
Power Down mode  
ODT  
timings to be applied.  
tAONPD max  
Internal  
Term Res.  
RTT  
Figure 17. Bank activate command cycle (tRCD=3, AL=2, tRP=3, tRRD=2, tCCD=2)  
T0  
T1  
T2  
T3  
Tn  
Tn+1  
Tn+2  
Tn+3  
CK#  
CK  
Internal RAS# - CAS# delay (>=tRCD min  
)
Bank A  
Row Addr.  
Bank A  
Col. Addr.  
Bank B  
Row Addr.  
Bank B  
Col. Addr  
Bank A  
Addr.  
Bank B  
Addr.  
Bank A  
Row Addr.  
ADDRESS  
CAS# - CAS# delay time (tCCD  
)
Additive latency delay (AL)  
tRCD = 1  
Read Begins  
RAS# - RAS# delay time (>=tRRD  
)
Bank A  
Post CAS#  
Read  
Bank B  
Post CAS#  
Read  
Bank A  
Activate  
Bank B  
Activate  
Bank A  
Precharge  
Bank B  
Precharge  
Bank A  
Activate  
COMMAND  
Bank Active (>=tRAS  
)
Bank precharge time (>=tRP)  
RAS# Cycle time (>=tRC  
)
Rev. 1.3  
41  
Oct. /2015  
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