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EM68C08CWAE-3H 参数 Datasheet PDF下载

EM68C08CWAE-3H图片预览
型号: EM68C08CWAE-3H
PDF下载: 下载PDF文件 查看货源
内容描述: [128M x 8 bit DDRII Synchronous DRAM (SDRAM)]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 63 页 / 512 K
品牌: ETRON [ ETRON TECHNOLOGY, INC. ]
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EtronTech  
EM68C08CWAE  
- tJIT(per), tJIT(per,lck)  
tJIT(per) is defined as the largest deviation of any single tCK from tCK(avg).  
tJIT(per) = Min/max of {tCKi- tCK(avg) where i=1 to 200}  
tJIT(per) defines the single period jitter when the DLL is already locked.  
tJIT(per,lck) uses the same definition for single period jitter, during the DLL locking period only.  
tJIT(per) and tJIT(per,lck) are not guaranteed through final production testing.  
- tJIT(cc), tJIT(cc,lck)  
tJIT(cc) is defined as the difference in clock period between two consecutive clock cycles:  
tJIT(cc) = Max of |tCKi+1 – tCKi  
|
tJIT(cc) defines the cycle to cycle jitter when the DLL is already locked.  
tJIT(cc,lck) uses the same definition for cycle to cycle jitter, during the DLL locking period only.  
tJIT(cc) and tJIT(cc,lck) are not guaranteed through final production testing.  
- tERR(2per), tERR (3per), tERR (4per), tERR (5per), tERR (6-10per) and tERR (11-50per)  
tERR is defined as the cumulative error across multiple consecutive cycles from tCK(avg).  
n=2  
n=3  
n=4  
n=5  
for  
for  
for  
for  
2per  
3per  
4per  
5per  
(
(
(
(
(
)
)
)
)
tERR  
tERR  
tERR  
tERR  
tERR  
tERR  
i +N1  
nper =  
N ×  
(
avg  
CK  
where  
(
)
(
)
)
∑  
tERR  
t
t
CKj  
j =1  
6 n 10 for  
6 10per  
)
11n 50 for  
1150per  
(
)
NOTE 34: These parameters are specified per their average values, however it is understood that the following  
relationship between the average timing and the absolute instantaneous timing holds at all times. (Min  
andmax of SPEC values are to be used for calculations in the table below.)  
Table 31. Absolute clock period average values  
Parameter  
Symbol  
Min.  
Max.  
Units  
Absolute clock period  
tCK (abs)  
tCK(avg),min + tJIT(per),min  
tCK(avg),max + tJIT(per),max  
ps  
Absolute clock HIGH pulse width tCH (abs) tCH(avg),min * tCK(avg),min + tCH(avg),max * tCK(avg),max + ps  
tJIT(duty),min tJIT(duty),max  
tCL (abs) tCL(avg),min * tCK(avg),min + tCL(avg), max * tCK(avg),max  
tJIT(duty),min + tJIT(duty), max  
Absolute clock LOW pulse width  
ps  
NOTE 35:tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not an  
input specification parameter. It is used in conjunction with tQHS to derive the DRAM output timing tQH. The  
value to be used for tQH calculation is determined by the following equation;  
tHP = Min ( tCH(abs), tCL(abs) ),  
where,  
tCH(abs) is the minimum of the actual instantaneous clock HIGH time;  
tCL(abs) is the minimum of the actual instantaneous clock LOW time;  
NOTE 36: tQHS accounts for:  
1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the input  
is transferred to the output; and  
2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next  
transition, both of which are independent of each other, due to data pin skew, output pattern effects, and  
p-channel to n-channel variation of the output drivers  
Rev. 1.3  
34  
Oct. /2015  
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