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EM68C08CWAE-3H 参数 Datasheet PDF下载

EM68C08CWAE-3H图片预览
型号: EM68C08CWAE-3H
PDF下载: 下载PDF文件 查看货源
内容描述: [128M x 8 bit DDRII Synchronous DRAM (SDRAM)]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 63 页 / 512 K
品牌: ETRON [ ETRON TECHNOLOGY, INC. ]
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EtronTech  
EM68C08CWAE  
Timing Waveforms  
Figure 8. Initialization sequence after power-up  
tCH tCL  
CK  
CK#  
tIS  
CKE  
ODT  
tIS  
EMR  
S
ANY  
CMD  
EMR  
S
EMR  
S
PRE  
ALL  
PRE  
ALL  
REF  
REF  
MRS  
NOP  
MRS  
Command  
Follow OCD Flowchart  
tRFC  
400ns  
tRP  
tMRD  
tMRD  
tRP  
tRFC  
tMRD  
tOIT  
OCD  
OCD  
Default  
DLL  
ENABLE  
DLL  
RESET  
CAL.MOD  
E EXIT  
min 200 Cycle  
NOTE 1: To guarantee ODT off, VREF must be valid and a LOW level must be applied to the ODT pin.  
Figure 9. OCD drive mode  
OCD calibration mode exit  
EMRS  
Enter Drive mode  
EMRS  
NOP  
NOP  
NOP  
CMD  
CK#  
CK  
Hi-Z  
Hi-Z  
DQS  
DQS HIGH & DQS# LOW for Drive(1), DQS LOW & DQS# HIGH for Drive(0)  
DQS#  
DQs HIGH for Drive(1)  
DQs LOW for Drive(0)  
DQ  
tOIT  
tOIT  
NOTE : Drive mode, both Drive(1) and Drive(0), is used for controllers to measure DDR2 SDRAM Driver  
impedance.In this mode, all outputs are driven out tOIT after "enter drive mode" command and all output  
drivers are turned-off tOIT after "OCD calibration mode exit" command.  
Rev. 1.3  
36  
Oct. /2015  
 复制成功!