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EM68C08CWAE-3H 参数 Datasheet PDF下载

EM68C08CWAE-3H图片预览
型号: EM68C08CWAE-3H
PDF下载: 下载PDF文件 查看货源
内容描述: [128M x 8 bit DDRII Synchronous DRAM (SDRAM)]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 63 页 / 512 K
品牌: ETRON [ ETRON TECHNOLOGY, INC. ]
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EtronTech  
EM68C08CWAE  
Table 27. Electrical Characteristics and Recommended A.C. Operating Conditions  
(VDD = 1.8V ± 0.1V, TOPER = 0 ~ 85°C)  
-18  
-25  
-3  
Specific  
Notes  
Symbol  
Parameter  
Unit  
Min.  
5
Max.  
8
Min  
5
Max.  
8
8
Min.  
5
Max.  
8
8
15, 33, 34  
15, 33, 34  
15, 33, 34  
15, 33, 34  
15, 33, 34  
34, 35  
CL=3  
CL=4  
CL=5  
CL=6  
CL=7  
ns  
ns  
ns  
ns  
ns  
tCK  
tCK  
3.75  
3
7.5  
3.75  
2.5  
2.5  
-
3.75  
3
tCK(avg)  
Average clock period  
7.5  
8
8
2.5  
7.5  
8
3
8
1.875  
0.48  
0.48  
7.5  
-
-
-
tCH(avg)  
tCL(avg)  
Average clock HIGH pulse width  
Average Clock LOW pulse width  
0.52  
0.52  
0.48  
0.48  
0.52  
0.52  
0.48  
0.48  
0.52  
0.52  
34, 35  
Write command to DQS associated clock  
edge  
DQS latching rising transitions to  
associated clock edges  
WL  
RL-1  
RL-1  
RL-1  
tCK  
tCK  
28  
28  
tDQSS  
-0.25  
0.25  
-0.25  
0.25  
-0.25  
0.25  
tDSS  
DQS falling edge to CK setup time  
DQS falling edge hold time from CK  
DQS input HIGH pulse width  
DQS input LOW pulse width  
Write preamble  
0.2  
0.2  
-
0.2  
0.2  
-
0.2  
0.2  
-
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
tDSH  
-
-
-
-
-
-
tDQSH  
tDQSL  
tWPRE  
tWPST  
0.35  
0.35  
0.35  
0.4  
0.35  
0.35  
0.35  
0.4  
0.35  
0.35  
0.35  
0.4  
-
-
-
-
-
-
10  
Write postamble  
0.6  
0.6  
0.6  
5, 7, 9,  
22, 27  
tIS(base)  
tIH(base)  
tIPW  
Address and Control input setup time  
Address and Control input hold time  
0.125  
0.2  
-
-
-
-
-
-
0.175  
0.25  
0.6  
-
-
-
-
-
-
0.2  
-
-
-
-
-
-
ns  
ns  
tCK  
ns  
ns  
tCK  
5, 7, 9,  
23, 27  
0.275  
0.6  
Control & Address input pulse width for  
each input  
0.6  
6-8, 20,  
26, 29  
tDS(base) DQ & DM input setup time  
tDH(base) DQ & DM input hold time  
0
0.05  
0.125  
0.35  
0.1  
6-8, 21,  
26, 29  
0.075  
0.35  
0.175  
0.35  
DQ and DM input pulse width for each  
input  
tDIPW  
38  
38  
tAC  
DQ output access time from CK, CK#  
DQS output access time from CK, CK#  
-0.35  
0.35  
-0.4  
0.4  
-0.45  
-0.4  
0.45  
0.4  
ns  
ns  
tDQSCK  
-0.325  
0.325  
-0.35  
0.35  
Data-out high-impedance time from CK,  
CK#  
DQS(DQS#) low-impedance time from  
CK, CK#  
DQ low-impedance time from CK, CK#  
18, 38  
tHZ  
-
t
t
AC(max)  
AC(max)  
-
t
t
AC(max)  
AC(max)  
-
t
t
AC(max) ns  
AC(max) ns  
tLZ(DQS)  
18, 38  
18, 38  
13  
t
AC(min)  
t
AC(min)  
t
AC(min)  
tLZ(DQ)  
tDQSQ  
2tAC(min) tAC(max) 2tAC(min) tAC(max) 2tAC(min) tAC(max) ns  
DQS-DQ skew for DQS and associated  
DQ signals  
-
0.175  
-
-
0.2  
-
-
0.24  
-
ns  
ns  
min  
(tCH,tCL  
min  
(tCH,tCL  
min  
(tCH,tCL)  
11, 12, 35  
tHP  
CK half pulse width  
)
)
tQHS  
tQH  
12, 36  
37  
DQ hold skew factor  
-
0.25  
-
0.3  
-
-
0.34  
ns  
ns  
tCK  
tCK  
ns  
ns  
tCK  
ns  
DQ/DQS output hold time from DQS  
Read preamble  
tHP -tQHS  
0.9  
0.4  
7.5  
35  
-
tHP -tQHS  
0.9  
0.4  
7.5  
35  
tHP -tQHS  
0.9  
-
19, 39  
19, 40  
4, 30  
tRPRE  
tRPST  
tRRD  
tFAW  
tCCD  
tWR  
1.1  
1.1  
0.6  
1.1  
Read postamble  
0.6  
0.4  
0.6  
Active to active command period  
Four Activate Window  
-
-
-
-
-
7.5  
-
-
-
-
-
37.5  
2
CAS# to CAS# command delay  
Write recovery time  
2
2
-
-
30  
15  
15  
15  
Auto Power write recovery + precharge  
time  
Internal Write to Read Command Delay  
Internal read to precharge command  
delay  
14, 31  
3, 24, 30  
3, 30  
tDAL  
tWTR  
tRTP  
WR + tRP  
7.5  
-
-
-
WR + tRP  
7.5  
-
-
-
WR + tRP  
7.5  
-
-
-
ns  
ns  
ns  
7.5  
7.5  
7.5  
Rev. 1.3  
27  
Oct. /2015  
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