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EM68C08CWAE-3H 参数 Datasheet PDF下载

EM68C08CWAE-3H图片预览
型号: EM68C08CWAE-3H
PDF下载: 下载PDF文件 查看货源
内容描述: [128M x 8 bit DDRII Synchronous DRAM (SDRAM)]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 63 页 / 512 K
品牌: ETRON [ ETRON TECHNOLOGY, INC. ]
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EtronTech  
EM68C08CWAE  
Table 22. AC overshoot/undershoot specification for clock, data, strobe, and mask pins  
(DQ, DQS, DQS#, DM, CK, CK#)  
Parameter  
-18  
0.5  
-25  
0.5  
-3  
Unit  
V
Maximum peak amplitude allowed for overshoot area  
Maximum peak amplitude allowed for undershoot area  
Maximum overshoot area above VDD  
0.5  
0.5  
0.5  
0.5  
V
0.19  
0.19  
0.23  
0.23  
0.23  
0.23  
V-ns  
V-ns  
Maximum undershoot area below VSS  
Table 23. Output AC test conditions  
Symbol  
Parameter  
Value  
Unit Note  
VOTR  
Output timing measurement reference level  
0.5xVDDQ  
V
1
NOTE1: The VDDQ of the device under test is referenced.  
Table 24. Output DC current drive  
Symbol  
IOH(dc)  
IOL(dc)  
Parameter  
SSTL_18  
-13.4  
Unit Note  
1, 3, 4  
Output minimum source DC current  
mA  
2, 3, 4  
Output minimum sink DC current  
13.4  
mA  
NOTE1: VDDQ = 1.7 V; VOUT = 1420 mV. (VOUT - VDDQ) /IOH must be less than 21 for values of VOUT between VDDQ  
and VDDQ - 280 mV.  
NOTE2: VDDQ = 1.7 V; VOUT = 280 mV. VOUT/IOL must be less than 21 for values of VOUT between 0 V and 280 mV.  
NOTE3: The dc value of VREF applied to the receiving device is set to VTT  
NOTE4: The values of IOH (dc) and IOL (dc) are based on the conditions given in Notes 1 and 2. They are used to  
test device drive current capability to ensure VIH min plus a noise margin and VIL max minus a noise  
margin are delivered to an SSTL_18 receiver. The actual current values are derived by shifting the desired  
driver operating point (see JEDEC standard: Section 3.3 of JESD8-15A) along a 21 load line to define a  
convenient driver current for measurement.  
Table 25. Capacitance  
(VDD = 1.8V, f = 1MHz, TOPER = 25°C)  
-18/25  
-3  
Symbol  
Parameter  
Min.  
Unit  
Max.  
1.75  
2.0  
Min.  
1.0  
1.0  
2.5  
-
Max.  
2.0  
Input Capacitance : Command and Address  
Input Capacitance (CK, CK#)  
CIN  
CCK  
1.0  
pF  
pF  
pF  
pF  
pF  
pF  
1.0  
2.0  
DM, DQ, DQS Input/Output Capacitance  
Delta Input Capacitance: Command and Address  
Delta Input Capacitance: CK, CK#  
CI/O  
2.5  
3.5  
3.5  
DCIN  
DCCK  
DCIO  
-
-
-
0.25  
0.25  
0.5  
0.25  
0.25  
0.5  
-
Delta Input/Output Capacitance: DM, DQ, DQS  
-
NOTE: These parameters are periodically sampled and are not 100% tested.  
Rev. 1.3  
25  
Oct. /2015  
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