EtronTech
EM68C08CWAE
Table 26. IDD specification parameters and test conditions
(VDD = 1.8V ± 0.1V, TOPER = 0 ~ 85°C)
-18
65
-25
-3
46
58
Parameter & Test Condition
Symbol
Unit
Max.
Operating one bank active-precharge current:
CK =tCK (min), tRC = tRC (min), tRAS = tRAS(min); CKE is HIGH, CS# is HIGH
between valid commands; Address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
Operating one bank active-read-precharge current:
t
IDD0
55
70
mA
I
OUT = 0mA; BL = 4, CL = CL (min), AL = 0; tCK = tCK (min),tRC = tRC (min), tRAS
IDD1
80
mA
= tRAS(min), tRCD = tRCD (min);CKE is HIGH, CS# is HIGH between valid
commands;Address bus inputs are switching; Data pattern is same as IDD4W
Precharge power-down current:
All banks idle;tCK =tCK (min); CKE is LOW; Other control and address bus IDD2P
inputs are STABLE; Data bus inputs are FLOATING
Precharge quiet standby current:
10
23
30
9
9
mA
mA
mA
All banks idle; tCK =tCK (min); CKE is HIGH, CS# is HIGH; Other control
and address bus inputs are STABLE; Data bus inputs are FLOATING
Precharge standby current:
IDD2Q
18
25
15
21
All banks idle; tCK = tCK (min); CKE is HIGH, CS# is HIGH; Other control and IDD2N
address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Active power-down current:
MRS(A12)=0
25
20
23
16
23
16
mA
mA
All banks open; tCK =tCK (min); CKE is LOW; Other
IDD3P
control and address bus inputs are STABLE; Data bus
MRS(A12)=1
inputs are FLOATING
Active standby current:
All banks open; tCK = tCK(min), tRAS = tRAS (max), tRP = tRP (min); CKE is
HIGH, CS# is HIGH between valid commands; Other control and address
bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating burst write current:
All banks open,continuous burst writes; BL = 4, CL = CL (min), AL = 0;
tCK= tCK (min), tRAS = tRAS (max), tRP = tRP (min); CKE is HIGH, CS# is HIGH IDD4W
between valid commands; Address bus inputs are switching; Data bus
inputs are switching
IDD3N
37
32
27
96
mA
mA
150
115
Operating burst read current:
All banks open, continuous burst reads, IOUT = 0mA; BL = 4, CL = CL (min),
AL = 0; tCK = tCK (min), tRAS = tRAS (max), tRP = tRP (min); CKE is HIGH, CS# IDD4R
is HIGH between valid commands; Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
135
100
84
mA
Burst refresh current:
t
CK = tCK (min); refresh command at every tRFC (min) interval; CKE is HIGH,
IDD5
125
10
100
9
84
9
mA
mA
CS# is HIGH between valid commands; Other control and address bus
inputs are SWITCHING; Data bus inputs are SWITCHING
Self refresh current:
CK and CK# at 0V; CKE ≤ 0.2V;Other control and address bus inputs are IDD6
FLOATING; Data bus inputs are FLOATING
Operating bank interleave read current:
All bank interleaving reads, IOUT= 0mA; BL = 4, CL = CL (min), AL =tRCD (min)
- 1 x tCK (min); tCK = tCK (min), tRC = tRC (min), tRRD = tRRD (min), tRCD = tRCD
(min); CKE is HIGH, CS# is HIGH between valid commands; Address bus
inputs are STABLE during DESELECTs.Data pattern is same as IDD4R
IDD7
215
180
150 mA
NOTE 1: IDD specifications are tested after the device is properly initialized.
NOTE 2: Input slew rate is specified by AC Parametric Test Condition.
NOTE 3: IDD parameters are specified with ODT disabled.
NOTE 4: Data bus consists of DQ, DM, DQS, DQS#. IDD values must be met with all combinations of EMRS bits 10 and 11.
NOTE 5: LOW = VIN ≦VILAC(max), HIGH = VIN ≧VIHAC(min), STABLE = inputs stable at a HIGH or LOW level, FLOATING = inputs at VREF =
VDDQ/2, SWITCHING = inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control
signals, and inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including masks or strobes.
Rev. 1.3
26
Oct. /2015
ETRON [ ETRON TECHNOLOGY, INC. ]
