EM68932DVKB
EtronTech
Table 11. D.C. Characteristics
(VDD=1.7V~1.95V, TA =-25~85°C)
-6
-75
Parameter & Test Condition
Symbol
Unit
Max.
Operating one bank active-precharge current:
IDD0
45
0.1
0.1
15
8
40
0.1
0.1
15
8
mA
tRC=tRC(min); tCK=tCK(min); CKE is HIGH; CS is HIGH between valid
commands; Address inputs are SWITCHING; data bus inputs are STABLE
Precharge power-down standby current:
IDD2P
IDD2PS
IDD2N
mA
mA
mA
mA
mA
mA
mA
mA
All banks idle, CKE is LOW; CS is HIGH, tCK=tCK(min);
address and control inputs are SWITCHING; data bus inputs are STABLE
Precharge power-down standby current with clock stop:
All banks idle, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH;
address and control inputs are SWITCHING; data bus inputs are STABLE
Precharge non power-down standby current:
All banks idle, CKE is HIGH; CS is HIGH, tCK=tCK(min);
address and control inputs are SWITCHING; data bus inputs are STABLE
Precharge non power-down standby current with clock stop:
IDD2NS
IDD3P
All banks idle, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH;
address and control inputs are SWITCHING; data bus inputs are STABLE
Active power-down standby current:
3
3
One bank active, CKE is LOW; CS is HIGH, tCK=tCK(min);
address and control inputs are SWITCHING; data bus inputs are STABLE
Active power-down standby current with clock stop:
IDD3PS
IDD3N
2
2
One bank active, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH;
address and control inputs are SWITCHING; data bus inputs are STABLE
Active non power-down standby current:
20
10
20
10
One bank active, CKE is HIGH; CS is HIGH, tCK=tCK(min) address and
control inputs are SWITCHING; data bus inputs are STABLE
Active non power-down standby current with clock stop:
IDD3NS
One bank active, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH;
address and control inputs are SWITCHING; data bus inputs are STABLE
Operating burst read current:
One bank active; BL = 4; CL = 3; tCK=tCK(min); continuous read bursts; IOUT = IDD4R
0 mA address inputs are SWITCHING; 50% data change each burst transfer
Operating burst write current:
150
150
70
130
130
70
mA
mA
mA
One bank active; BL = 4; tCK=tCK(min); continuous write bursts;
address inputs are SWITCHING; 50% data change each burst transfer
Auto-Refresh current:
IDD4W
tRFC = tRFC(min); tCK=tCK(min); burst refresh; CKE is HIGH;
IDD5
address and control inputs are SWITCHING; data bus inputs are STABLE
Self refresh current:
℃
µA
µA
µA
µA
TCSR Range
Max. 40 Max.85
CKE is LOW, CK = LOW, CK = HIGH; Extended Mode
Full Array
Register set to all address and control inputs are STABLE;
data bus inputs are STABLE
160
110
90
200
150
120
IDD6
IDD8
1/2 Full Array
1/4 Full Array
10
Deep Power Down Mode Current
Note:
1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage of the
device.
2. All voltages are referenced to VSS.
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the
minimum value of tCK and tRC. Input signals are changed one time per two clock cycles.
Etron Confidential
15
Rev. 1.0
Aug. 2009
ETRON [ ETRON TECHNOLOGY, INC. ]
