EM68932DVKB
EtronTech
z Burst Interruption
Read Interrupted by Read
Burst Read can be interrupted before completion of the burst by a new Read command to any bank. When
the previous burst is interrupted, data bits from the remaining addresses are overridden by data from the
new addresses with the full burst length. The data from the previous Read command continues to appear
on the outputs until the CAS latency from the interrupting Read command is satisfied. At this point the data
from the interrupting Read command appears. The Read to Read interval is a minimum of 1 clock.
Read Interrupted by Burst Stop & Write
To interrupt Burst Read with a write command, the Burst Stop command must be asserted to avoid data
contention on the I/O bus by placing the DQ (output drivers) in a high impedance state. To ensure the DQ
are tri-stated one cycle before the beginning of the write operation, the Burst Stop command must be
applied at least 2 clock cycles for CL = 2 and at least 3 clock cycles for CL = 3 before the Write command.
Read Interrupted by Precharge
Burst Read can be interrupted by a Precharge of the same bank. A minimum of 1 clock cycle is required for
the read precharge interval. A Precharge command to output disable latency is equivalent to the
latency.
CAS
Write Interrupted by Write
A Burst Write can be interrupted by the new Write command before completion of the previous Burst Write,
with the only restriction being that the interval that separates the commands must be at least one clock
cycle. When the previous burst is interrupted, the remaining addresses are overridden by the new
addresses and the new data will be written into the device until the programmed Burst Length is satisfied.
Write Interrupted by Read & DM
A Burst Write can be interrupted by a Read command to any bank. The DQ must be in the high impedance
state at least one clock cycle before the interrupting read data appears on the outputs to avoid data
contention. When the Read command is to be asserted, any residual data from the Burst Write sequence
must be masked by DM. The delay from the last data to the Read command (tWTR) is required to avoid data
contention inside the DRAM. Data presented on the DQ pins before the Read command is initiated will
actually be written to the memory. A Read command interrupting a write sequence can not be issued at the
next clock edge following the Write command.
Write Interrupted by Precharge & DM
A Burst Write can be interrupted by a Precharge of the same bank before completion of the previous burst.
A write recovery time (tWR) is required from the last data to the Precharge command. When the Precharge
command is asserted, any residual data from the Burst Write cycle must be masked by DM.
z Burst Stop Command
The Burst Stop command is initiated by having
and
High with
and
Low at the rising
WE
RAS
CAS
CS
edge of the clock only. The Burst Stop command has the fewest restrictions, making it the easiest method
to use when terminating a burst operation before it has been completed. When the Burst Stop command is
issued during a Burst Read cycle, both the data and DQS (Data Strobe) go to a high impedance state after
a delay which is equal to the
latency set in the Mode Register. The Burst Stop command, however, is
CAS
not supported during a Burst Write operation.
Etron Confidential
11
Rev. 1.0
Aug. 2009
ETRON [ ETRON TECHNOLOGY, INC. ]
