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EM68932DVKB-6H 参数 Datasheet PDF下载

EM68932DVKB-6H图片预览
型号: EM68932DVKB-6H
PDF下载: 下载PDF文件 查看货源
内容描述: 4M ×32的移动DDR同步DRAM (SDRAM)的 [4M x 32 Mobile DDR Synchronous DRAM (SDRAM)]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 40 页 / 342 K
品牌: ETRON [ ETRON TECHNOLOGY, INC. ]
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EM68932DVKB  
EtronTech  
Table 12. Electrical AC Characteristics  
(VDD=1.7V~1.95V, TA =-25~85°C)  
-6  
-75  
Symbol  
Parameter  
Unit Note  
Min.  
12  
Max.  
-
Min.  
12  
Max.  
-
1
CL = 2  
CL = 3  
ns  
tCK  
Clock cycle time  
1
6
100  
0.55  
0.55  
5.5  
7.5  
0.45  
0.45  
2
100  
0.55  
0.55  
6
ns  
tCH  
Clock high level width  
0.45  
0.45  
2
tCK  
tCK  
ns  
tCL  
Clock low level width  
DQS-out access time from CK,  
tDQSCK  
CK  
Output access time from CK,  
2
3
tAC  
2
-
5.5  
0.5  
1.1  
0.6  
1.25  
-
2
-
6
0.6  
1.1  
0.6  
1.25  
-
ns  
ns  
CK  
tDQSQ  
tRPRE  
tRPST  
tDQSS  
DQS-DQ Skew  
Read preamble  
Read postamble  
CK to valid DQS-in  
0.9  
0.4  
0.75  
0
0.9  
0.4  
0.75  
0
tCK  
tCK  
tCK  
ns  
tWPRES DQS-in setup time  
tWPRE  
tWPST  
tDQSH  
tDQSL  
DQS write preamble  
0.25  
0.4  
0.4  
0.4  
-
0.25  
0.4  
0.4  
0.4  
-
tCK  
tCK  
tCK  
tCK  
DQS write postamble  
0.6  
0.6  
0.6  
0.6  
0.6  
0.6  
DQS in high level pulse width  
DQS in low level pulse width  
1
tIS  
Address and Control input setup time  
Address and Control input hold time  
DQ & DM setup time to DQS  
1.1  
1.1  
0.6  
0.6  
-
-
-
-
1.3  
1.3  
0.8  
0.8  
-
-
-
-
ns  
ns  
ns  
ns  
1
tIH  
4, 5  
4, 5  
tDS  
tDH  
tHP  
DQ & DM hold time to DQS  
tCLMIN or  
tCHMIN  
tHP  
tCLMIN or  
tCHMIN  
tHP  
Clock half period  
-
-
-
-
ns  
ns  
tQH  
Output DQS valid window  
0.65  
0.75  
67.5  
110  
45  
tRC  
tRFC  
tRAS  
tRCD  
tRP  
Row cycle time  
60  
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tCK  
tCK  
tCK  
tCK  
ns  
ns  
µs  
Refresh row cycle time  
Row active time  
110  
42  
-
-
100K  
100K  
ACTIVE to READ or WRITE delay  
Row precharge time  
18  
-
22.5  
22.5  
15  
-
18  
-
-
tRRD  
twR  
Row active to Row active delay  
Write recovery time  
12  
-
-
8
7
12  
-
15  
-
tDAL  
tWTR  
tCCD  
tMRD  
tXSR  
tXP  
Auto precharge write recovery + Precharge time tWR+tRP  
-
tWR+tRP  
1
-
Internal Write to Read Delay  
2
1
-
-
Col. Address to Col. Address delay  
Mode register set cycle time  
-
1
-
2
-
2
-
Self refresh exit to next valid command delay  
Exit Power Down mode to first valid command  
Refresh interval time  
200  
25  
-
-
-
200  
25  
-
-
6
tREFI  
Note:  
15.6  
-
15.6  
1. Table 13.Input Setup / Hold Slew Rate Derating  
Input Setup/Hold Slew Rate (V/ns)  
tIH (ps)  
tIS (ps)  
0
1.0  
0.8  
0.6  
0
+50  
+50  
+100  
+100  
This derating table is used to increase tIS / tIH in the case where the input slew rate is below 1.0V/ns.  
Etron Confidential  
16  
Rev. 1.0  
Aug. 2009