EtronTech
EM68916CWQA
NOTE 4: Differential data strobe
DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on
the Setting of the EMRS “Enable DQS” mode bit; timing advantages of differential mode are realized in
system design. The method by which the DDR2 SDRAM pin timings are measured is mode dependent. In
single ended mode, timing relationships are measured relative to the rising or falling edges of DQS
crossing at VREF. In differential mode, these timing relationships are measured relative to the crosspoint of
DQS and its complement, DQS#. This distinction in timing methods is guaranteed by design and
characterization. Note that when differential data strobe mode is disabled via the EMRS, the
complementary pin, DQS#, must be tied externally to VSS through a 20 ꢀ to 10 kꢀ resistor to insure
proper operation.
NOTE 5: AC timings are for linear signal transitions.
NOTE 6:All voltages are referenced to VSS.
NOTE 7:These parameters guarantee device behavior, but they are not necessarily tested on each
device.They may be guaranteed by device design or tester correlation
NOTE 8: Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal
reference/supply voltage levels, but the related specifications and device operation are guaranteed for the
full voltage range specified.
Specific notes for dedicated AC parameters
NOTE 1:User can choose which active power down exit timing to use via MRS (bit 12). tXARD is expected to be
used for fast active power down exit timing. tXARDS is expected to be used for slow active power down exit
timing where a lower power value is defined by each vendor data sheet.
NOTE 2: AL=Additive Latency.
NOTE 3:This is a minimum requirement. Minimum read to precharge timing is AL+BL/2 provided that the tRTP
and tRAS (min) have been satisfied.
NOTE 4: A minimum of two clocks (2* tCK) is required irrespective of operating frequency.
NOTE 5: Timings are specified with command/address input slew rate of 1.0 V/ns.
NOTE 6:Timings are specified with DQs, DM, and DQS’s (in single ended mode) input slew rate of 1.0V/ns.
NOTE 7:Timings are specified with CK/CK# differential slew rate of 2.0 V/ns. Timings are guaranteed for DQS
signals with a differential slew rate of 2.0 V/ns in differential strobe mode and a slew rate of 1 V/ns in
single ended mode.
NOTE 8:The maximum limit for this parameter is not a device limit. The device will operate with a greater value
for this parameter, but system performance (bus turnaround) will degrade accordingly.
NOTE 9:MIN (tCL, tCH) refers to the smaller of the actual clock LOW time and the actual clock HIGH time as
provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH).
NOTE 10: tQH = tHP – tQHS, where:
tHP = minimum half clock period for any given cycle and is defined by clock HIGH or clock LOW (tCH, tCL).
tQHS accounts for:
1) The pulse duration distortion of on-chip clock circuits; and
2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next
transition, both of which are, separately, due to data pin skew and output pattern effects, and p-
channel to n-channel variation of the output drivers.
NOTE 11: tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of
the output drivers as well as output slew rate mismatch between DQS / DQS# and associated DQ in any
given cycle.
NOTE 12: tDAL = WR + RU{ tRP[ns] / tCK[ns] }, where RU stands for round up.WR refers to the tWR parameter
stored in the MRS. For tRP, if the result of the division is not already an integer, round up to the next
highest integer. tCK refers to the application clock period.
NOTE 13: The clock frequency is allowed to change during self–refresh mode or precharge power-down mode.
In case of clock frequency change during precharge power-down.
Etron Confidential
29
Rev. 1.1
Apr. 2009
ETRON [ ETRON TECHNOLOGY, INC. ]
