EtronTech
EM68916CWQA
Table 26. IDD specification parameters and test conditions
(VDD = 1.8V ± 0.1V, TOPR = 0~85 °C)
-25
-3
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Parameter & Test Condition
Symbol
Unit
Max.
Operating one bank active-precharge current:
t
CK =tCK (min), tRC = tRC (min), tRAS = tRAS(min); CKE is HIGH,
IDD0
90
90
85
mA
CS# is HIGH between valid commands; Address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
Operating one bank active-read-precharge current:
IOUT = 0mA; BL = 4, CL = CL (min), AL = 0; tCK = tCK (min),tRC =
tRC (min), tRAS = tRAS(min), tRCD = tRCD (min);CKE is HIGH, CS# is
HIGH between valid commands;Address bus inputs are
switching; Data pattern is same as IDD4W
IDD1
115
100
100
mA
Precharge power-down current:
All banks idle;tCK =tCK (min); CKE is LOW; Other control and IDD2P
address bus inputs are STABLE; Data bus inputs are FLOATING
Precharge quiet standby current:
10
40
10
40
10
35
mA
mA
All banks idle; tCK =tCK (min); CKE is HIGH, CS# is HIGH; Other
IDD2Q
control and address bus inputs are STABLE; Data bus inputs are
FLOATING
Precharge standby current:
All banks idle; tCK = tCK (min); CKE is HIGH, CS# is HIGH; Other
control and address bus inputs are SWITCHING; Data bus
IDD2N
45
45
35
mA
inputs are SWITCHING
Active power-down current:
MRS(A12)=0
35
15
30
12
30
12
mA
mA
All banks open; tCK =tCK (min); CKE is LOW; Other
IDD3P
control and address bus inputs are STABLE; Data
MRS(A12)=1
bus inputs are FLOATING
Active standby current:
All banks open; tCK = tCK(min), tRAS = tRAS (max), tRP = tRP (min);
CKE is HIGH, CS# is HIGH between valid commands; Other IDD3N
control and address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
64
55
50
mA
mA
Operating burst write current:
All banks open,continuous burst writes; BL = 4, CL = CL (min),
AL = 0; tCK= tCK (min), tRAS = tRAS (max), tRP = tRP (min); CKE is IDD4W
HIGH, CS# is HIGH between valid commands; Address bus
inputs are switching; Data bus inputs are switching
Operating burst read current:
200
180
170
All banks open, continuous burst reads, IOUT = 0mA; BL = 4, CL
= CL (min), AL = 0; tCK = tCK (min), tRAS = tRAS (max), tRP = tRP
(min); CKE is HIGH, CS# is HIGH between valid commands;
IDD4R
175
160
150
mA
Address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
Burst refresh current:
tCK = tCK (min); refresh command at every tRFC (min) interval; CKE
is HIGH, CS# is HIGH between valid commands; Other control IDD5B
and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
180
5
170
5
170
5
mA
mA
Self refresh current:
CK and CK# at 0V; CKE ≤ 0.2V;Other control and address bus IDD6
inputs are FLOATING; Data bus inputs are FLOATING
Operating bank interleave read current:
All bank interleaving reads, IOUT= 0mA; BL = 4, CL = CL (min),
AL =tRCD (min) - 1 x tCK (min); tCK = tCK (min), tRC = tRC (min), tRRD
= tRRD (min), tRCD = tRCD (min); CKE is HIGH, CS# is HIGH
IDD7
265
240
235
mA
between valid commands; Address bus inputs are STABLE
during DESELECTs.Data pattern is same as IDD4R
Etron Confidential
25
Rev. 1.1
Apr. 2009
ETRON [ ETRON TECHNOLOGY, INC. ]
