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EM68916CWQA-37H 参数 Datasheet PDF下载

EM68916CWQA-37H图片预览
型号: EM68916CWQA-37H
PDF下载: 下载PDF文件 查看货源
内容描述: 8M ×16位DDRII同步DRAM ( SDRAM ) [8M x 16 bit DDRII Synchronous DRAM (SDRAM)]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 59 页 / 1180 K
品牌: ETRON [ ETRON TECHNOLOGY, INC. ]
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EtronTech  
EM68916CWQA  
Table 27. Electrical Characteristics and Recommended A.C. Operating Conditions  
(VDD = 1.8V ± 0.1V, TOPR = 0~85 °C)  
-25  
-3  
-37  
Specific  
Notes  
Symbol  
Parameter  
Unit  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
CL=3  
CL=4  
CL=5  
CL=6  
-
-
8
-
-
8
5
3.75  
-
8
13, 31, 32  
13, 31, 32  
13, 31, 32  
13, 31, 32  
32, 33  
ns  
ns  
ns  
ns  
tCK  
tCK  
tCK  
3.75  
3
3.75  
3
8
-
tCK  
Clock cycle time  
8
8
2.5  
0.48  
0.48  
8
-
-
-
-
Average clock HIGH pulse width  
Average Clock LOW pulse width  
0.52  
0.52  
0.48  
0.48  
0.52  
0.52  
0.45  
0.45  
0.55  
0.55  
tCH(avg)  
tCL(avg)  
WL  
32, 33  
Write command to DQS associated clock edge  
RL-1  
RL-1  
RL-1  
DQS latching rising transitions to associated clock  
edges  
-0.25  
0.25  
-0.25  
0.25  
-0.25  
0.25  
26  
26  
tDQSS  
tCK  
DQS falling edge to CK setup time  
DQS falling edge hold time from CK  
0.2  
0.2  
-
-
0.2  
0.2  
-
-
0.2  
0.2  
-
-
tDSS  
tDSH  
tCK  
tCK  
DQS input HIGH pulse width  
0.35  
-
0.35  
-
0.35  
-
tDQSH  
tCK  
DQS input LOW pulse width  
Write preamble  
0.35  
0.35  
0.4  
-
-
0.35  
0.35  
0.4  
-
-
0.35  
0.35  
0.4  
-
-
tDQSL  
tWPRE  
tWPST  
tCK  
tCK  
tCK  
Write postamble  
0.6  
0.6  
0.6  
8
5, 7, 20,  
25  
Address and Control input setup time  
0.175  
-
0.2  
-
0.25  
-
tIS(base)  
ns  
5, 7, 21,  
25  
Address and Control input hold time  
0.25  
0.6  
-
-
-
0.275  
0.6  
-
-
-
0.375  
0.6  
-
-
-
tIH(base)  
tIPW  
ns  
tCK  
ns  
Control & Address input pulse width for each input  
DQ & DM input setup time (differential strobe)  
6, 7, 18,  
24, 27  
0.05  
0.1  
0.1  
tDS(base)  
6, 7,  
19,24, 27  
DQ & DM input hold time (differential strobe)  
0.125  
-
0.175  
-
0.225  
-
tDH(base)  
ns  
DQ and DM input pulse width for each input  
DQ output access time from CK, CK#  
0.35  
-0.4  
-0.35  
-
-
0.35  
-0.45  
-0.4  
-
-
0.35  
-0.5  
-0.45  
-
-
tDIPW  
tAC  
tDQSCK  
tHZ  
tLZ(DQS)  
tLZ(DQ)  
tDQSQ  
tHP  
tCK  
ns  
ns  
0.4  
0.35  
0.45  
0.4  
0.5  
0.45  
36  
36  
DQS output access time from CK, CK#  
Data-out high-impedance time from CK, CK#  
DQS(DQS#) low-impedance time from CK, CK#  
DQ low-impedance time from CK, CK#  
16, 36  
16, 36  
16, 36  
11  
tAC(max)  
tAC(max)  
tAC(max) ns  
tAC(min) tAC(max) tAC(min) tAC(max) tAC(min) tAC(max) ns  
2tAC(min)  
2tAC(min)  
2tAC(min)  
tAC(max)  
0.2  
tAC(max)  
0.24  
tAC(max) ns  
0.3  
DQS-DQ skew for DQS and associated DQ signals  
-
-
-
ns  
min(tCL,tC  
min(tCL,tC  
Min  
(tCL,tCH  
CK half pulse width  
-
-
-
9, 10, 33  
ns  
)
)
)
H
H
DQ hold skew factor  
-
tHP -tQHS  
0.9  
0.3  
-
tHP -tQHS  
0.9  
0.34  
-
0.4  
10, 34  
35  
tQHS  
tQH  
ns  
ns  
DQ/DQS output hold time from DQS  
Read preamble  
-
-
tHP -tQHS  
-
1.1  
1.1  
0.9  
0.4  
1.1  
17, 37  
17, 38  
4, 28  
tRPRE  
tRPST  
tRRD  
tCCD  
tWR  
tCK  
Read postamble  
0.4  
0.6  
0.4  
0.6  
0.6  
tCK  
Active to active command period  
CAS# to CAS# command delay  
Write recovery time  
7.5  
-
-
-
-
-
-
-
-
7.5  
-
-
-
-
-
-
-
-
7.5  
-
ns  
2
2
2
-
tCK  
15  
15  
15  
-
28  
12, 29  
3, 22, 28  
3, 28  
23  
ns  
Auto Power write recovery + precharge time  
Internal Write to Read Command Delay  
Internal read to precharge command delay  
CKE minimum pulse width  
WR + tRP  
7.5  
WR + tRP  
7.5  
WR + tRP  
7.5  
-
tDAL  
tWTR  
tRTP  
tCKE  
tXSNR  
tXSRD  
tXP  
ns  
-
ns  
7.5  
7.5  
7.5  
-
ns  
3
3
3
-
tCK  
Exit self refresh to non-read command delay  
Exit self refresh to a read command  
Exit precharge power down to any command  
-
28  
t
t
t
ns  
RFC+10  
200  
2
RFC+10  
200  
2
RFC+10  
200  
2
-
-
-
-
-
tCK  
-
tCK  
Etron Confidential  
26  
Rev. 1.1  
Apr. 2009  
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