Et r on Tech
EM669325
4M x 32 LPSDRAM
Figure 11.1. Random Row Read (Interleaving Banks)
(Burst Length=8, CAS# Latency=1)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
tCK1
High
CS#
RAS#
CAS#
WE#
BA0,1
RBx
RBx
RAx
RAx
RBy
RBy
A10
CBy
CBx
A0~A11
CAx
tRCD
tRP
tAC1
DQM
DQ
Hi-Z
By0
By1
By2
Bx6
Bx0
Bx1 Bx2 Bx3 Bx4 Bx5
Bx7
Ax0 Ax1 Ax2 Ax3
Ax4
Ax5 Ax6 Ax7
Activate
Precharge
Read
Command
Bank B
Precharge
Comm and
Bank A
Activate
Comm and
Bank A
Comm and
Comm and
Bank B
Bank B
Activate
Comm and
Bank B
Read
Read
Command
Bank B
Command
Bank A
Preliminary
37
Rev 0.6
Sep. 2003