Et r on Tech
EM669325
4M x 32 LPSDRAM
Figure 10.2. Random Column Write (Page within same Bank)
(Burst Length=4, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
RBz
RBz
RBw
RBw
CBy
CBw
A0~A11
DQM
CBz
CBx
DBz0
Write
Hi-Z
DQ
DBz2 DBz3
DBz1
DBy0
DBw0 DBwD1Bw2 DBw3 DBx0 DBx1
DBy1
DBy2 DBy3
Activate
Write
Write
Command
Bank B
Write
Command
Bank B
Precharge Activate
Command Command
Command Command
Command
Bank B
Bank A
Bank B
Bank B
Bank B
Preliminary
35
Rev 0.6
Sep. 2003