Et r on Tech
EM669325
4M x 32 LPSDRAM
Figure 10.3. Random Column Write (Page within same Bank)
(Burst Length=4, CAS# Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RBz
RBz
RBw
RBw
CBx
CBy
CBw
A0~A11
DQM
CBz
Hi-Z
DBy0
DBz0
Write
DBz2
DQ
DBw0 DBw1DBw2 DBw3 DBx0 DBx1
DBy1 DBy2 DBy3
DBz1
Activate
Command
Bank A
Write
Command
Bank B
Write
Comm and Command
Bank B Bank B
Write
Precharge
Comm and
Bank B
Activate
Comm and
Bank B
Command
Bank B
Preliminary
36
Rev 0.6
Sep. 2003