Et r on Tech
EM669325
4M x 32 LPSDRAM
Figure 7.3. Clock Suspension During Burst Write (Using CKE)
(Burst Length=4, CAS# Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
tCK3
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A11
RAx
CAx
DQM
DQ
Hi-Z
DAx0
DAx2
DAx3
DAx1
Activate
Command
Bank A
Clock Suspend Clock Suspend
1 Cycle 2 Cycles
Write
Command
Bank A
Clock Suspend
3 Cycles
Note:
CKE to CLK disable/enable = 1 clock
Preliminary
29
Rev 0.6
Sep. 2003