Et r on Tech
EM669325
4M x 32 LPSDRAM
Figure 6.2. Clock Suspension During Burst Read (Using CKE)
(Burst Length=4, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
tCK2
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A11
DQM
CAx
RAx
tHZ
Hi-Z
DQ
Ax3
Ax0
Ax1
Ax2
Clock Suspend
2 Cycles
Activate
Command
Bank A
Read
Comm and
Bank A
Clock Suspend
1 Cycle
Clock Suspend
3 Cycles
Note:
CKE to CLK disable/enable = 1 clock
Preliminary
25
Rev 0.6
Sep. 2003