Et r on Tech
EM669325
4M x 32 LPSDRAM
Figure 8. Power Down Mode and Clock Mask (Burst Lenght=4, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
tCK2
tPDE
tIS
Valid
RAS#
CAS#
WE#
BS0,1
A10
RAx
CAx
RAx
A0~A11
DQM
tHZ
Hi-Z
Ax0
Ax1
Ax3
Ax2
DQ
ACTIVE
STANDBY
PRECHARGE
STANDBY
Activate
Command
Bank A
Read
Command
Bank A
Clock Mask
Start
Clock Mask
End
Precharge
Command
Bank A
Power Down
Mode Exit
Any
Power Down
ModeEntry
Power Down
Mode Exit
Command
Power Down
ModeEntry
Preliminary
30
Rev 0.6
Sep. 2003