Et r on Tech
EM669325
4M x 32 LPSDRAM
Figure 4. Power on Sequene and Auto Refresh (CBR)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
tCK2
High level
is reauired
Minimum of 2 Refresh Cycles are required
CS#
RAS#
CAS#
WE#
BA0,1
A10
Address Key
A0-A11
DQM
DQ
tRP
tRC
Hi-Z
PrechargeALL
Command
1st AutoRefresh
Command
2nd Auto Refresh
Command
Any
Command
Mode Register
Set Command
Inputs must be
stable for 200 µs
Preliminary
22
Rev 0.6
Sep. 2003