Et r on Tech
EM669325
4M x 32 LPSDRAM
Figure 6.1. Clock Suspension During Burst Read (Using CKE)
(Burst Length=4, CAS# Latency=1)
T0 T 1 T2 T3 T4 T5 T6
T
7
T8 T9 T10 T 11 T1 T13 T14 T15 T16 T17 T1 T19 T20 T21 T22
CLK
tCK1
CKE
CS#
RAS#
CAS#
WE#
BA0,1
RAx
A10
A0-A11
RAx CAx
DQM
DQ
tHZ
Ax3
Hi-Z
Ax0
Ax1
Ax2
Activate
Command
Bank A
Clock Suspend
1 Cycle
Clock Suspend
2 Cycles
Clock Suspend
3 Cycles
Read
Command
Bank A
Note:
CKE to CLK disable/enable = 1 clock
Preliminary
24
Rev 0.6
Sep. 2003