Et r on Tech
EM669325
4M x 32 LPSDRAM
Note:
1
2
Power-up sequence is described in Note 7.
A.C. Test Conditions
LVTTL Interface
Reference Level of Output Signals
1.4V/1.4V
Output Load
Reference to the Under Output Load (B)
Input Signal Levels (VIH/VIL)
2.4V/0.4V
1ns
Transition Time (Rise and Fall) of Input Signals
Reference Level of Input Signals
1.4V
3.3V
3.0V
1.4V
50Ω
1.2kΩ
50Ω
Z0=
Output
Output
30pF
30pF
870Ω
LVTTL D.C. Test Load (A)
LVTTL A.C. Test Load (B)
3. Transition times are measured between VIH and VIL. Transition(rise and fall) of input signals are in a fixed
slope (1 ns).
4. tHZ defines the time in which the outputs achieve the open circuit condition and are not at reference levels.
5. If clock rising time is longer than 1 ns, ( tR / 2 -0.5) ns should be added to the parameter.
6. Assumed input rise and fall time tT ( tR & tF ) = 1 ns
If tR or tF is longer than 1 ns, transient time compensation should be considered, i.e., [(tr + tf)/2 - 1] ns
should be added to the parameter.
7. Power up Sequence
Power up must be performed in the following sequence.
1) Power must be applied to VDD and VDDQ(simultaneously) when all input signals are held "NOP" state
and both CKE = "H" and DQM = "H." The CLK signals must be started at the same time.
2) After power-up, a pause of 200µ seconds minimum is required. Then, it is recommended that DQM
is held "HIGH" (VDD levels) to ensure DQ output is in high impedance.
3) All banks must be precharged.
4) Mode Register Set command must be asserted to initialize the Mode register.
5) A minimum of 2 Auto-Refresh dummy cycles must be required to stabilize the internal circuitry of the
device.
Preliminary
18
Rev 0.6
Sep. 2003
ETRON [ ETRON TECHNOLOGY, INC. ]
