EM639165
WRITE
the last input data to the PRE command, the write recovery
time (tWR) is required. When A10 is high at a WRITE
command, the autoprecharge (WRITEA) is performed. Any
command (READ, WRITE, PRE, TBST, ACT) to the same
bank is inhibited till the internal precharge is complete. The
internal precharge begins at tWR after the last input data
cycle. (Need to keep tRAS min.) The next ACT command
can be issued after tRP from the internal precharge timing.
After tRCD from the bank activation, a WRITE command
can be issued. 1st input data is set at the same cycle as the
WRITE. Following (BL -1) data are written into the RAM,
when the Burst Length is BL. The start address is specified
by A0-A9,A11(x4), A0-9(X8), A0-8(X16) and the address
sequence of burst data is defined by the Burst Type. A
WRITE command may be applied to any active bank, so
the row precharge time (tRP) can be hidden behind con-
tinuous input data by interleaving the multiple banks. From
WRITE with Auto-Precharge (BL=4)
CLK
ACT
Xa
Write ACT
Write PRE
PRE
Command
A0-9
tRCD
tRCD
Y
0
Xb
Xb
Xb
10
Y
Xa
Xa
0
0
0
0
A10
Xa
Xa
0
A11
00
00
10
00
10
BA0,1
DQ
Da0 Da1
Da2 Da3 Db0 Db1 Db2 Db3
Multi Bank Interleaving WRITE (BL=4)
CLK
ACT
Xa
Write
ACT
Xa
Command
A0-9
tRCD
tRP
Y
A10
A11
Xa
1
Xa
Xa
Xa
00
00
00
BA0,1
DQ
tWR
Da0 Da1
Da2 Da3
Internal precharge starts
Preliminary
Rev 1.0 Feb. 2001
17
ETRON [ ETRON TECHNOLOGY, INC. ]
