EM639165
MODE REGISTER
POWER ON SEQUENCE
Burst Length, Burst Type and /CAS Latency can be pro-
grammed by setting the mode register (MRS). The mode
register stores these data until the next MRS command,
which may be issued when all banks are in idle state. After
tRSC from a MRS command, the SDRAM is ready for new
command.
Before starting normal operation, the following power on
sequence is necessary to prevent a SDRAM from damaged
or malfunctioning.
1. Apply power and start clock. Attempt to maintain CKE
high, DQM high and NOP condition at the inputs.
2. Maintain stable power, stable clock, and NOP input con-
ditions for a minimum of 200µs.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or
more auto-refresh commands.
5. Issue a mode register set command to initialize the mode
register.
CLK
/CS
/RAS
/CAS
/WE
After these sequence, the SDRAM is idle state and ready
for normal operation.
V
BA0,1 A11-A0
BA0 BA1 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0
0
0
0
0
0
0
LTMODE
BT
BL
BL
BT= 0
BT= 1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
1
2
1
2
CL
/CAS LATENCY
4
4
BURST
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
R
R
2
8
8
LENGTH
R
R
R
FP
R
R
R
R
LATENCY
3
MODE
R
R
R
R
BURST
TYPE
0
1
SEQUENTIAL
INTERLEAVED
R: Reserved for Future Use
FP: Full Page
Preliminary
Rev 1.0 Feb. 2001
13
ETRON [ ETRON TECHNOLOGY, INC. ]
