EM638165
EtronTech
Figure 34. Interleaved Column Write Cycle
(Burst Length=4)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
RAx
RBw
A0-A9,
A11
CAx RBw
CBw
CBx
CBy
CAy
CBz
tWR
tWR
tRCD
DQM
DQ
tRRD>tRRD (min)
DAx0 DAx1 DAx2 DAx3 DBw0 DBw1 DBx0 DBx1 DBy0 DBy1 DAy0 DAy1 DBz0 DBz1 DBz2 DBz3
Hi-Z
Write
Command
Bank B
Precharge
Command
Bank B
Activate
Command
Bank A
Write
Command
Bank A
Write
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
Write
Command
Bank A
Activate
Precharge
Command
Bank B
Command
Bank A
Don’t Care
Rev. 5.2
40
Rev. 5.2
Dec. /2013