EM638165
EtronTech
Figure 32.2. Read and Write Cycle
(Burst Length=4, CAS# Latency=3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A9,
A11
RAx
CAx
CAy
CAz
DQM
DQ
Hi-Z
Ax0
Ax1
Ax2
Ax3
DAy0 DAy1
DAy3
Az0
Az1
Az3
The Write Data
The Read Data
is Masked with a
Two Clock
Activate
Command
Bank A
Read
Command
Bank A
Write
Command
Bank A
is Masked with a
Zero Clock
Read
Command
Bank A
Latency
Latency
Don’t Care
Rev. 5.2
37
Rev. 5.2
Dec. /2013